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    Oscillation and rotation metric controller
    82.
    发明授权
    Oscillation and rotation metric controller 失效
    振荡和旋转度量控制器

    公开(公告)号：US07429980B2

    公开(公告)日：2008-09-30

    申请号：US10991419

    申请日：2004-11-19

    Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

    Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

    IPC: G09G5/00 ,  G09G5/08 ,  G06F3/033 ,  G01B7/14 ,  G01B7/30 ,  G01R33/06 ,  H01L43/06

    CPC classification number: G06F3/0383 ,  G01D5/145 ,  G06F3/0362

    Abstract: An oscillation and rotation metric controller comprised of a scrolling wheel mechanism to oscillate for driving magnetic poles of a permanent magnet to displace thus to generate signals of changed magnetic field, signals being retrieved to achieve lateral oscillation metric control; and a knob switch encoder being fixed to the scrolling wheel mechanism to execute metric control by rotation displacement.

    Abstract translation: 振荡和旋转度量控制器包括滚动轮机构，用于振荡以驱动永磁体的磁极，从而移位，从而产生改变的磁场的信号;检索信号以实现横向振荡度量控制; 以及旋钮开关编码器，其被固定到滚动轮机构，以通过旋转位移执行度量控制。

    Dual metal silicides for lowering contact resistance
    83.
    发明申请
    Dual metal silicides for lowering contact resistance 有权
    双金属硅化物，用于降低接触电阻

    公开(公告)号：US20080145984A1

    公开(公告)日：2008-06-19

    申请号：US11640713

    申请日：2006-12-18

    Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

    Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

    IPC: H01L21/8234

    CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

    Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

    Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极电极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

    Strained silicon MOS devices
    86.
    发明授权
    Strained silicon MOS devices 有权
    应变硅MOS器件

    公开(公告)号：US07342289B2

    公开(公告)日：2008-03-11

    申请号：US10637351

    申请日：2003-08-08

    Applicant: Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

    Inventor： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

    IPC: H01L29/76

    CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

    Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

    Abstract translation: 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

    Transistor with a strained region and method of manufacture
    87.
    发明授权
    Transistor with a strained region and method of manufacture 有权
    具有应变区域的晶体管及其制造方法

    公开(公告)号：US07335929B2

    公开(公告)日：2008-02-26

    申请号：US10967917

    申请日：2004-10-18

    Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    IPC: H01L31/00

    CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

    Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

    Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

    Offset spacer formation for strained channel CMOS transistor
    88.
    发明授权
    Offset spacer formation for strained channel CMOS transistor 有权
    用于应变通道CMOS晶体管的偏移间隔物形成

    公开(公告)号：US07321155B2

    公开(公告)日：2008-01-22

    申请号：US10840911

    申请日：2004-05-06

    Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    IPC: H01L29/772

    CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

    Abstract: A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

    Abstract translation: 应变沟道晶体管及其形成方法，所述应变沟道晶体管包括半导体衬底; 覆盖沟道区的栅极电介质; 覆盖栅极电介质的栅电极; 源极扩展（SDE）区域和源极和漏极（S / D）区域; 其特征在于，设置有选自由邻近所述栅电极配置的一对应力偏置间隔物和设置在包括所述S / D区域的所述栅极上方的应力介电层的应力电介质部分，以在沟道区域上施加应变。

    High performance CMOS with metal-gate and Schottky source/drain
    90.
    发明申请
    High performance CMOS with metal-gate and Schottky source/drain 有权
    具有金属栅极和肖特基源极/漏极的高性能CMOS

    公开(公告)号：US20060273409A1

    公开(公告)日：2006-12-07

    申请号：US11134897

    申请日：2005-05-23

    Applicant: Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

    Inventor： Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

    IPC: H01L29/76

    CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/32155 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66643

    Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 Å on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 Å.

    Abstract translation: 提供了具有金属/金属硅化物栅极和肖特基源极/漏极的半导体器件及其形成方法。 半导体器件包括覆盖半导体衬底的栅极电介质，金属或金属硅化物栅电极，其功函数小于约4.3eV或大于约4.9eV，覆盖在栅极电介质上，具有小于约100的厚度的间隔物 并且肖特基源/漏极具有小于约4.3eV或大于约4.9eV的功函数，其中肖特基源极/漏极区与栅电极重叠。 肖特基源极/漏极区优选具有小于约的厚度。

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