公开(公告)号：US08703617B2

公开(公告)日：2014-04-22

申请号：US13147044

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

摘要翻译： 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US08664119B2

公开(公告)日：2014-03-04

申请号：US13497526

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

IPC分类号： H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823807 ,  H01L29/66545

摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

摘要翻译： 一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层 在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层 和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

公开(公告)号：US20140048765A1

公开(公告)日：2014-02-20

申请号：US13812500

申请日：2012-10-12

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L29/0895 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7391 ,  H01L29/7835 ,  H01L29/7848

摘要： The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that the source region in the source and drain regions comprises GeSn alloy, and a tunnel dielectric layer is optionally comprised between the GeSn alloy of the source region and the channel region. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn alloy having a narrow band gap is formed by implanting precursors and performing a laser rapid annealing, the on-state current of TFET is effectively enhanced, accordingly it has an important application prospect in a high performance low power consumption application.

摘要翻译： 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源极和漏极区中的源极区包括GeSn合金，并且隧道电介质层任选地包含在源极区的GeSn合金和沟道区之间。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火来形成具有窄带隙的GeSn合金，有效地提高了TFET的通态电流，因此具有 在高性能低功耗应用中的重要应用前景。

公开(公告)号：US08652893B2

公开(公告)日：2014-02-18

申请号：US13510439

申请日：2011-11-25

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

摘要翻译： 一种半导体器件及其制造方法，其中NMOS器件由通过PECVD具有高紫外光吸收系数的氮化硅膜覆盖，所述氮化硅膜在被受激光激光表面退火时可以很好地吸收紫外光，因此 为了达到良好的脱氢效果，脱氢后，氮化硅膜具有较高的拉伸应力; 由于氮化硅膜具有高的紫外光吸收系数，因此不需要加热基板，从而避免了由于将基板加热脱氢而导致的对器件的不利影响，并且保持了由PECVD工艺引起的热量预算。

公开(公告)号：US20140027857A1

公开(公告)日：2014-01-30

申请号：US13812498

申请日：2012-08-27

申请人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7848

摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate stack structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, characterized in that each of the first gate stack structures comprises a first gate insulating layer, a first blocking layer, a first work function regulating layer and a resistance regulating layer, and each of the second gate stack structures comprises a second gate insulating layer, a first blocking layer, a second work function regulating layer, a first work function regulating layer and a resistance regulating layer.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极堆叠结构包括多个第一栅极叠层结构和多个第二栅极堆叠结构，其特征在于，每个第一栅极堆叠结构包括第一栅极绝缘层，第一阻挡层 ，第一功函数调节层和电阻调节层，并且每个第二栅极堆叠结构包括第二栅极绝缘层，第一阻挡层，第二功函数调节层，第一功函数调节层和电阻调节 层。

公开(公告)号：US20140017906A1

公开(公告)日：2014-01-16

申请号：US13695191

申请日：2012-07-26

申请人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

发明人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/02

CPC分类号： H01L21/02186 ,  C23C14/0641 ,  C23C14/18 ,  C23C14/34 ,  C23C14/54 ,  H01L21/2855

摘要： A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.

摘要翻译： 公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下，通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在电场加速后，用惰性气体的离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场中在晶片的表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入晶片的表面，使得应力被引入到氮化钛层中，其中非晶化部分 通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。 在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在 氮化钛层增加。

公开(公告)号：US20130240996A1

公开(公告)日：2013-09-19

申请号：US13520611

申请日：2012-04-11

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层 ，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节 掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节 工作功能准确。

公开(公告)号：US20130105906A1

公开(公告)日：2013-05-02

申请号：US13496477

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： The present invention relates to a CMOS device having dual metal gates and a method of manufacturing the same. The device comprising: a semiconductor substrate; a first-type MOS device comprising a first gate stack and a second-type MOS device comprising a second gate stack and having an opposite conductivity type, the first-type MOS device and the second-type MOS device being formed on the substrate; wherein the first gate stack is comprised of a first gate insulating layer, a first work function regulating layer formed on the first gate insulating layer and applicable to the first-type MOS device, and a first filling metal layer surrounded by the first work function regulating layer from the bottom and sides, and the second gate stack is comprised of a second gate insulating layer, a second work function regulating layer formed on the second gate insulating layer and applicable to the second-type MOS device, and a second filling metal layer surrounded by the second function regulating layer from the bottom and sides.

摘要翻译： 本发明涉及具有双金属栅极的CMOS器件及其制造方法。 该装置包括：半导体衬底; 包括第一栅极堆叠和第二类型MOS器件的第一型MOS器件，所述第一栅极堆叠和包括第二栅极堆叠并具有相反导电类型的第二类型MOS器件，所述第一类型MOS器件和所述第二类型MOS器件形成在所述衬底上; 其中所述第一栅极堆叠包括第一栅极绝缘层，形成在所述第一栅极绝缘层上并适用于所述第一类型MOS器件的第一功函数调节层，以及由所述第一功函数调节包围的第一填充金属层 并且第二栅极堆叠包括第二栅极绝缘层，形成在第二栅极绝缘层上并可应用于第二类型MOS器件的第二功函数调节层和第二填充金属层 由第二功能调节层从底部和侧面包围。

公开(公告)号：US20130005127A1

公开(公告)日：2013-01-03

申请号：US13322473

申请日：2011-07-27

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/283

CPC分类号： H01L29/66795

摘要： A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.

摘要翻译： 提供了一种制造多栅装置的方法，包括：提供半导体衬底; 蚀刻半导体衬底以形成突出的鳍; 在鳍片的底部蚀刻半导体衬底，以在翅片和半导体衬底之间形成间隙; 形成覆盖所述半导体基板和所述翅片并填充所述间隙的电介质层; 并蚀刻该电介质层以暴露该翅片的顶部和一部分侧壁。 本发明可以通过简单的工艺实现翅片之间的隔离，成本相对较低，适合大规模的工业应用。

公开(公告)号：US08324061B2

公开(公告)日：2012-12-04

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。