公开(公告)号：US07839242B1

公开(公告)日：2010-11-23

申请号：US11893535

申请日：2007-08-16

申请人： Peter J. Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Trevor Niblock ,  Peter Johnson ,  Vladislav Vashchenko

IPC分类号： H01H51/34

CPC分类号： H02M3/34

摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.

摘要翻译： MEMS磁通开关被制造为铁磁芯。 芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。 中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。

公开(公告)号：US07259411B1

公开(公告)日：2007-08-21

申请号：US10728132

申请日：2003-12-04

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

公开(公告)号：US07239712B1

公开(公告)日：2007-07-03

申请号：US10874451

申请日：2004-06-23

申请人： Robert Drury ,  Peter J. Hopper ,  Michael Mian ,  Peter Johnson

发明人： Robert Drury ,  Peter J. Hopper ,  Michael Mian ,  Peter Johnson

IPC分类号： H04R9/00

CPC分类号： H04R19/005 ,  H04R19/04

摘要： An inductor-based integrated MEMS microphone and a method of making the microphone is provided. The microphone structure includes a vibrating inductor that is suspended over another stationary inductor such that the magnetic field induced from one inductor induces an electrical potential across the other. The stationary inductor is embedded in a dielectric material that is etched out over the stationary inductor to provide the cavity over which the vibrating inductor is suspended.

摘要翻译： 提供基于电感器的集成MEMS麦克风和制造麦克风的方法。 麦克风结构包括悬挂在另一个固定电感器上的振动电感器，使得从一个电感器感应出的磁场引起跨越另一电感器的电位。 固定电感器被嵌入介电材料中，该绝缘材料在静电感应器上蚀刻出来，以提供振动电感器悬挂在其上的空腔。

公开(公告)号：US07119431B1

公开(公告)日：2006-10-10

申请号：US10665897

申请日：2003-09-18

申请人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Iouri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L23/34 ,  H01L27/12

CPC分类号： H01L29/78606 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

摘要翻译： 散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。 该装置包括形成在晶片的有源硅层中的晶体管。 活性表面形成在氧化物层和体硅层上。 在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。 在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。 塞子延伸穿过本体层的厚度到氧化物层。 此后，塞子填充有导热材料，例如金属或DAG（导热浆）。 在运行期间，来自晶体管的热量通过散热器消散。 在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

公开(公告)号：US06864581B1

公开(公告)日：2005-03-08

申请号：US10219212

申请日：2002-08-15

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Michael Mian ,  Robert Drury

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Michael Mian ,  Robert Drury

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.

摘要翻译： 以千兆赫兹频率的金属迹线的RF阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个指状物。 当形成为具有多个环时，金属迹线形成具有增加的Q的电感器。

公开(公告)号：US06707117B1

公开(公告)日：2004-03-16

申请号：US10285235

申请日：2002-10-31

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer ,  Andy Strachon ,  Peter Johnson

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer ,  Andy Strachon ,  Peter Johnson

IPC分类号： H01C2976

CPC分类号： H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.

摘要翻译： 在半导体结构中，单个器件或不同器件的区域之间的互连通过形成跨越要互连的区域的金属插塞来实现，其中插塞由在结构上形成硅化物层所用的金属形成。 在蚀刻之前，将金属掩盖在所需区域中，以留下金属塞。

公开(公告)号：US08531002B2

公开(公告)日：2013-09-10

申请号：US12899384

申请日：2010-10-06

申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

IPC分类号： H01L27/08

CPC分类号： H01L23/5227 ,  C23C28/023 ,  C25D5/022 ,  C25D7/123 ,  C25D17/001 ,  H01L27/0207 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

摘要翻译： 用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。 该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路和开关节点。 一旦制造晶片，则分别将多个电感器直接制造在晶片上的多个晶片上。 每个电感器通过在形成在晶片上的互连电介质层上形成多个磁芯电感器构件来制造。 然后在每个管芯上方的多个磁芯电感器部件上形成绝缘层，然后形成电感器线圈。 分别在多个电感器上形成电镀磁性层，以提高结构的磁导率和电感。

公开(公告)号：US07507589B1

公开(公告)日：2009-03-24

申请号：US11820921

申请日：2007-06-21

申请人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

发明人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

IPC分类号： H01L21/00

CPC分类号： H01F41/046 ,  H01F10/14 ,  H01F10/265 ,  H01F17/0033 ,  H01F41/309 ,  H01F2017/0066

摘要： A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

摘要翻译： 通过利用在磁芯结构周围形成的单个厚的宽的环形环来形成提供单位毫欧范围电阻的非常非常低的电阻微机电系统（MEMS）电感器。 磁芯结构又可以利用具有易轴和硬轴的叠层Ni-Fe结构。

公开(公告)号：US07435628B1

公开(公告)日：2008-10-14

申请号：US11881671

申请日：2007-07-27

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

公开(公告)号：US07351593B1

公开(公告)日：2008-04-01

申请号：US11137767

申请日：2005-05-25

申请人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

发明人： Peter Johnson ,  Peter J. Hopper ,  Kyuwoon Hwang ,  Robert Drury

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H02M7/003

摘要： A method is provided for forming the ferromagnetic core of an on-chip inductor structure. In accordance with the method, a static, permanent magnet is placed in proximity to a semiconductor wafer upon which the ferromagnetic core is being electroplated. The permanent magnet is place such that the magnetic field is orthogonal to the wafer. The “easy” axis material is that plated parallel parallel to the magnet's field and saturates at a lower applied field. The “hard” axis is that plated perpendicular to the applied magnetic filed and saturates later, at a higher current level. This plating approach results in optimum magnetic alignment of the ferromagnetic core so as to maximize both the field strength/magnetic flux slope and magnitude before magnetic material saturation occurs.

摘要翻译： 提供一种用于形成片上电感器结构的铁磁芯的方法。 根据该方法，将静电永磁体放置在电磁铁芯的半导体晶片附近。 永磁体的位置使得磁场与晶片正交。 “易”轴材料是平行于磁体的磁场平行并在较低的应用场饱和。 “硬”轴垂直于所施加的磁场进行电镀，并在较高的电流水平下饱和。 这种电镀方法导致铁磁芯的最佳磁对准，以便在磁性材料饱和发生之前使场强/磁通斜率和幅度最大化。