公开(公告)号：US20050074945A1

公开(公告)日：2005-04-07

申请号：US10710637

申请日：2004-07-27

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L23/544 ,  H01L21/8242 ,  H01L21/76

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A method of forming an overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material is formed over the first trench and the first deposition layer. A second trench is formed exposing the first deposition layer within the first trench. The second trench is partially filled with a second deposition layer forming a third trench. A third material layer is formed on the substrate to cover the second deposition layer and the second material layer. A step height is formed on the third deposition layer between the edge of the first trench and the center of the first trench. A raised feature serving as an inner mark is formed on the third deposition layer.

Abstract translation: 提供了一种形成覆盖标记的方法。 在基板上形成第一材料层，然后在第一材料层中形成用作沟槽型外标的第一沟槽。 第一沟槽部分地填充有第一沉积层。 在第一沟槽和第一沉积层上形成第二材料。 形成第二沟槽，使第一沉积层暴露在第一沟槽内。 第二沟槽部分地填充有形成第三沟槽的第二沉积层。 在基板上形成第三材料层以覆盖第二沉积层和第二材料层。 在第一沉积层的边缘和第一沟槽的中心之间的第三沉积层上形成台阶高度。 在第三沉积层上形成用作内标的凸起特征。

公开(公告)号：US06875659B2

公开(公告)日：2005-04-05

申请号：US10614698

申请日：2003-07-03

Applicant: Ta-Hung Yang ,  Ching-Yu Chang

Inventor： Ta-Hung Yang ,  Ching-Yu Chang

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/1126

Abstract: A method of code programming a mask read only memory (ROM) is disclosed. According to the method, a first photoresist layer is formed over word lines and a gate oxide layer of a substrate already having implanted bit lines. The first photoresist layer is patterned to develop pre-code openings over all of the memory cells, which correspond to intersecting word and bit lines. The first photoresist layer is then hardened using either a treatment implant or a treatment plasma. Subsequently, a second photoresist layer is formed over the first photoresist layer and patterned to develop real-code openings over memory cells which are actually to be coded with a logic “0” value. Each memory cell to be coded is then implanted with implants passing through the pre-code openings and the real code openings and into the memory cell.

Abstract translation: 公开了一种代码编程掩模只读存储器（ROM）的方法。 根据该方法，在字线和具有注入位线的衬底的栅极氧化物层上形成第一光致抗蚀剂层。 图案化第一光致抗蚀剂层以在对应于相交字和位线的所有存储单元上形成预编码开口。 然后使用处理植入物或处理等离子体硬化第一光致抗蚀剂层。 随后，在第一光致抗蚀剂层上形成第二光致抗蚀剂层，并将其图案化以在实际上以逻辑“0”值编码的存储器单元上形成实际代码开口。 然后，将通过预代码开口和实际代码开口的植入物植入待编码的每个存储单元并进入存储单元。

公开(公告)号：US06794280B2

公开(公告)日：2004-09-21

申请号：US10604587

申请日：2003-07-31

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L213205

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer comprising a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on each side of the longitudinal strip. The longitudinal strip is patterned to form a plurality of stacked blocks. Thereafter, a dielectric layer is formed over the substrate. The dielectric layer exposes the cap layer of the stacked blocks. Some cap layers of the stacked blocks are removed to expose the conductive layer underneath. A word line is formed over the dielectric layer to connect stacked blocks in the same row serially together.

Abstract translation: 提供了一种制造非易失性存储器的方法。 堆叠层的纵向条形成在衬底上。 纵向条是包括栅介电层，导电层和盖层的层叠层。 在纵向条的每一侧上的基板中形成掩埋位线。 图案化纵向条以形成多个堆叠的块。 此后，在衬底上形成电介质层。 电介质层暴露堆叠块的盖层。 去除堆叠块的一些盖层以露出下面的导电层。 在电介质层上形成一个字线，以将串联在同一行中的堆叠块连接起来。

公开(公告)号：US06787013B2

公开(公告)日：2004-09-07

申请号：US09949693

申请日：2001-09-10

Applicant: Ching-Yu Chang ,  Cherng-Jyh Lee ,  Tzer-Ming Chen

Inventor： Ching-Yu Chang ,  Cherng-Jyh Lee ,  Tzer-Ming Chen

IPC: G01N2726

CPC classification number: G01N33/5438 ,  A61B5/14532 ,  A61B2562/0295 ,  C12Q1/001 ,  Y10T29/49105 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A spacer forming method for a biosensor that has a biosensor possessing a capillary sampling channel and electrical connecting tracks for the use of a specific portable meter. A pair of electrodes is printed on an insulating base plate to be the transducer of the electrochemical biosensor by means of the screen-printing technology. The advanced thick-film printing technology is employed to construct the spacer component of the sampling channel that precisely controls the volume of a sample solution. Therefore, the spacer forming method reduces the usage of adhesive that otherwise causes a serious problem during a continuous punching procedure. Furthermore, the embedded switch pad on the biosensor is introduced to be instead of a micro switch in a connector of the portable meter.

Abstract translation: 一种用于生物传感器的间隔物形成方法，其具有具有毛细管取样通道的生物传感器和用于使用特定便携式仪表的电连接轨道。 通过丝网印刷技术将一对电极印刷在绝缘基板上作为电化学生物传感器的换能器。 采用先进的厚膜印刷技术构建了精确控制样品溶液体积的取样通道的间隔元件。 因此，间隔物形成方法减少了在连续冲压过程中导致严重问题的粘合剂的使用。 此外，引入生物传感器上的嵌入式开关板代替便携式仪表的连接器中的微型开关。

公开(公告)号：US06673682B2

公开(公告)日：2004-01-06

申请号：US10144874

申请日：2002-05-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L218236

CPC classification number: H01L27/11253 ,  H01L27/112 ,  H01L27/1126

Abstract: Methods for making integrated circuit devices, such as high density memory devices and memory devices exhibiting dual bits per cell, include forming multiple oxide fences on a semiconductor substrate between multiple polybars. The oxide fences create a hole pre-code pattern that facilitates ion implantation into trenches disposed between the polybars. The holes, or voids, formed by the oxide fences provide greater control of the critical dimension of ion implantation, for example, the critical dimension of the trench sidewalls. Semiconductor devices used in the manufacture of memory devices include the oxide fences during the manufacturing process.

Abstract translation: 用于制造诸如高密度存储器件和表现出每个单元双位的存储器件的集成电路器件的方法包括在多个多边形之间的半导体衬底上形成多个氧化物围栅。 氧化物栅栏产生一个孔预编码图案，便于将离子注入到设置在多边形之间的沟槽中。 由氧化物栅栏形成的孔或空隙提供了对离子注入的关键尺寸（例如沟槽侧壁的临界尺寸）的更大控制。 用于制造存储器件的半导体器件包括在制造过程中的氧化物栅栏。

公开(公告)号：US06607674B2

公开(公告)日：2003-08-19

申请号：US09726459

申请日：2000-11-30

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: B81B702

CPC classification number: C03C17/3649 ,  C03C17/3435 ,  C03C17/36 ,  C03C17/3665 ,  C03C2218/33 ,  G03F1/32 ,  G03F1/72

Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.

公开(公告)号：US06569761B2

公开(公告)日：2003-05-27

申请号：US09903667

申请日：2001-07-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L214763

CPC classification number: H01L21/0337 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/0338 ,  H01L21/76816

Abstract: In accordance with the present invention, a method is provided for shrinking critical dimension in semiconductor processes. This method comprises a step of performing an over-exposure process to a photosensitive layer to form a patterned photosensitive layer on a substrate by using a patterned reticle. Due to the unexposed region of the photosensitive layer being diminished by over-exposure the critical dimension is shrunk. Then, a sacrificial layer is applied for the purpose of pattern reverse-transferring. Next, the patterned photosensitive layer is removed such that the pattern is transferred to the sacrificial layer with a shrunk critical dimension. In cooperation of the present exposure technology with the present invention, the shrinkage of a critical dimension is accomplished, for example, using an I-line exposure light source in a critical dimension of 0.25 &mgr;m process, or using a deep UV (ultraviolet) exposure light source in a critical dimension of 0.13 &mgr;m process.

公开(公告)号：US06562691B2

公开(公告)日：2003-05-13

申请号：US09799003

申请日：2001-03-06

Applicant: Ching-Yu Chang ,  Wei-Hwa Sheu

Inventor： Ching-Yu Chang ,  Wei-Hwa Sheu

IPC: H01L2176

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A method for forming a protrusive alignment-mark in semiconductor devices is disclosed. A photolithography process is performed to form a photoresist layer on a substrate wherein the substrate has an element region and an alignment region, and the photoresist layer has an element photoresist region and an alignment photoresist region. Afterwards, a first dielectric layer is deposited on the element photoresist region and the alignment photoresist region. The excess portion of first dielectric layer above the photoresist layer is removed such that the photoresist layer is coplanar with the first dielectric layer and thus the photoresist layer is exposed. The photoresist layer on the element region and said alignment region is stripped to form a protrusive alignment-mark on the alignment region.

公开(公告)号：US06448605B1

公开(公告)日：2002-09-10

申请号：US09924904

申请日：2001-08-08

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2976

CPC classification number: H01L28/92 ,  H01L21/28273 ,  H01L21/32139 ,  H01L29/66545

Abstract: A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the substrate beside the lower portion of the floating gate. A conductive layer is formed on the first dielectric layer to completely fill the first opening. The conductive layer is patterned to form a second opening in the conductive layer. The second opening is above the first opening and does not expose the first dielectric layer. The second opening has a tapered sidewall and a predetermined depth. A mask layer is formed to cover the conductive layer and fill the second opening. The mask layer outside the second opening is removed to expose the conductive layer. A portion of the mask layer is removed to leave a first etching mask layer in the second opening. An anisotropic etching process using the first etching mask layer as a mask is performed to etch the conductive layer. An upper portion of the floating gate is formed. The first dielectric layer is exposed. The first etching mask is removed. Thereafter, a dielectric layer between gates and a control gate is formed over the floating gate.

公开(公告)号：US09851636B2

公开(公告)日：2017-12-26

申请号：US13542160

申请日：2012-07-05

Applicant: Chen-Yu Liu ,  Ching-Yu Chang

Inventor： Chen-Yu Liu ,  Ching-Yu Chang

IPC: G03F7/004 ,  G03F7/016 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/0045 ,  G03F7/0163 ,  G03F7/0382 ,  G03F7/0392

Abstract: A photosensitive material and methods of making a pattern on a substrate are disclosed. The photosensitive material includes a polymer that turns soluble to a developer solution after a chemically amplified reaction, and at least one chemical complex having a single diffusion length. The material includes at least one photo-acid generator (PAG) linked to at least one photo decomposable base (PDB) or quencher.