公开(公告)号：US08400915B1

公开(公告)日：2013-03-19

申请号：US12710592

申请日：2010-02-23

Applicant: David Alan Brown ,  Raghunath Reddy Kommidi ,  Sanjay T. Karambale

Inventor： David Alan Brown ,  Raghunath Reddy Kommidi ,  Sanjay T. Karambale

IPC: H04L12/26 ,  H04L12/54 ,  H04L12/56

CPC classification number: H04L47/39

Abstract: A packet switch includes a pipeline scheduler for scheduling packets according to a credit-based flow control protocol. A credit update pipeline stage initializes available credits for egress ports of the packet switch. A request pipeline stage generates packet requests for packets based on the available credits. A grant pipeline stage selects packets based on the ports requests and the available credits, and generates port grants for the selected packets. Additionally, the credit update stage updates the available credits based on the port grants. The packet switch routes the selected packets from ingress ports of the packet switch to the egress ports based on the port grants. In some embodiments, ingress ports generate enqueue requests based on the packets, an enqueue pipeline stage generates enqueue states based on the enqueue requests, and the request pipeline stage selects packets for routing based on the enqueue states and the available credits.

Abstract translation: 分组交换机包括用于根据基于信用的流控制协议来调度分组的流水线调度器。 信用更新流水线阶段初始化分组交换机出口端口的可用信用。 请求流水线阶段基于可用的信用来生成分组的分组请求。 授权流水线阶段基于端口请求和可用信用来选择分组，并为所选择的分组生成端口许可。 此外，信用更新阶段根据端口许可更新可用信用。 分组交换机基于端口授权，将选择的分组从分组交换机的入口端口路由到出口端口。 在一些实施例中，入口端口基于分组生成入队请求，入队流水线阶段基于入队请求生成入队状态，并且请求流水线级基于入队状态和可用信用来选择用于路由的分组。

公开(公告)号：US08390591B2

公开(公告)日：2013-03-05

申请号：US12975666

申请日：2010-12-22

Applicant: David Hann Jung

Inventor： David Hann Jung

IPC: G06F3/041

CPC classification number: G06F3/044

Abstract: A touch sensor is provided including a controller and a planar layout having an edge and an interior portion. Further including a connector coupling the touch controller to the layout; a substrate made of a first material; and sensing elements made of a second material formed on the substrate and covering the layout without overlapping. Sensing elements have non-monotonic widths from the center along two perpendicular directions, and a centroid. The touch sensor including pass-through traces to couple edge to interior portions to determine two-dimensional locations for touches using a weighting that is proportional to an overlap area of the sensor elements and their centroids. The substrate may be made of a dielectric and the sensing elements made of a conductor. A method for using a controller circuit having a memory to store centroid locations and determine a two-dimensional location on a touch screen as above is also provided.

Abstract translation: 提供了包括控制器和具有边缘和内部部分的平面布局的触摸传感器。 还包括将触摸控制器耦合到布局的连接器; 由第一材料制成的基板; 以及由形成在基板上并覆盖布局而不重叠的由第二材料制成的感测元件。 感测元件具有从中心沿着两个垂直方向和质心的非单调宽度。 触摸传感器包括用于将边缘连接到内部部分的直通轨迹，以使用与传感器元件的重叠区域和它们的质心成比例的加权来确定触摸的二维位置。 衬底可以由电介质制成，感测元件由导体制成。 还提供了一种使用具有存储器来存储重心位置并且如上所述确定触摸屏上的二维位置的控制器电路的方法。

公开(公告)号：US08386758B1

公开(公告)日：2013-02-26

申请号：US12511985

申请日：2009-07-29

Applicant: Victoria B. Mitchell ,  Ryan Paul Harvey ,  Ronald Jay Lisle ,  Vitaliy I. Kulikov

Inventor： Victoria B. Mitchell ,  Ryan Paul Harvey ,  Ronald Jay Lisle ,  Vitaliy I. Kulikov

IPC: G06F9/24 ,  G06F15/177

CPC classification number: G06F9/4411

Abstract: A computing system includes a codec device, a basic input-output system including both configuration data and feature data for the codec device, and a device driver for the codec device. The basic input-output system configures the codec device based on the configuration data. The device driver reads the feature data from the basic input-output system and enables one or more features of the codec device based on the feature data. In various embodiments, the device driver is WHQL certified and is included in an automated operating system upgrade of the computing system. Because the feature data is in the basic input-output system, the feature data is preserved during the operating system upgrade of the computing system. In some embodiments, the device driver enables one or more features of an application program based on the feature data.

Abstract translation: 计算系统包括编解码器装置，包括编解码装置的配置数据和特征数据的基本输入输出系统以及编解码装置的装置驱动器。 基本输入输出系统根据配置数据配置编解码器设备。 设备驱动程序从基本输入输出系统读取特征数据，并且基于特征数据启用编解码器设备的一个或多个特征。 在各种实施例中，设备驱动程序被WHQL认证，并被包括在计算系统的自动操作系统升级中。 由于特征数据位于基本输入输出系统中，因此在计算系统的操作系统升级期间会保留特征数据。 在一些实施例中，设备驱动器基于特征数据启用应用程序的一个或多个特征。

公开(公告)号：US08384431B2

公开(公告)日：2013-02-26

申请号：US12964246

申请日：2010-12-09

Applicant: Jeffrey G. Barrow

Inventor： Jeffrey G. Barrow

IPC: H03K19/0175 ,  H03L5/00

CPC classification number: H03K3/35613

Abstract: Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.

Abstract translation: 本文公开了电平移动电路和相关方法。 电平移位电路包括耦合到较高电源电压，输出信号和反相输出信号的交叉耦合上拉电路。 输入信号在接地和较低电源电压之间转变，反相输入信号在与地电位和较低电源电压之间的输入信号相反的方向上转变。 第一n沟道晶体管具有耦合到较低电源电压的栅极，耦合到输出信号的漏极和耦合到反相输入信号的源极。 第二n沟道晶体管具有耦合到较低电源电压的栅极，耦合到反相输出信号的漏极和耦合到输入信号的源极。 电平移位电路可以包括在具有第一电压域中的核心逻辑的IC中，以及在第二电压域中的输入/输出逻辑。

公开(公告)号：US08378864B2

公开(公告)日：2013-02-19

申请号：US13049728

申请日：2011-03-16

Applicant: Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

Inventor： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/468

Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

Abstract translation: 逐次近似公开了模数转换器（ADC）及相关方法。 逐次逼近ADC包括具有比较器输出的比较器和耦合到公共模型信号和比较输入的输入。 控制逻辑产生响应于比较器输出的一个或多个控制信号。 电容器阵列包括可操作地耦合到阵列输出的电容器的第一侧。 电容器阵列响应于一个或多个控制信号选择性地将电容器的第二侧的每一个耦合到模拟输入信号和一个或多个输入参考信号。 电压限制器可操作地耦合在阵列输出和比较器的比较输入之间，并将比较输入端的电压限制在相对于阵列输出的预定范围内。 逐次逼近ADC也可以与第二比较器和第二限压器差分地配置。

公开(公告)号：US20120302194A1

公开(公告)日：2012-11-29

申请号：US13114960

申请日：2011-05-24

Applicant: Suresh Atluri ,  Liang Leon Zhang

Inventor： Suresh Atluri ,  Liang Leon Zhang

IPC: H04B1/16

CPC classification number: H04L12/10

Abstract: A method and apparatus for an equalized On-Die Termination (ODT) circuit uses timed switching to reduce receiver power consumption.

Abstract translation: 用于均衡的片上终端（ODT）电路的方法和装置使用定时切换来减少接收机功率消耗。

公开(公告)号：US20120299617A1

公开(公告)日：2012-11-29

申请号：US13114970

申请日：2011-05-24

Applicant: Liang Leon Zhang ,  Suresh Atluri ,  Yue Yu ,  Al Xuefeng Fang

Inventor： Liang Leon Zhang ,  Suresh Atluri ,  Yue Yu ,  Al Xuefeng Fang

IPC: H03K19/003

CPC classification number: H03K19/018521 ,  H04L25/0298

Abstract: A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption.

Abstract translation: 使用有源组件的低功率AC在线终端（ODT）电路的方法和装置降低了接收机的功耗。

公开(公告)号：US08319540B2

公开(公告)日：2012-11-27

申请号：US12803681

申请日：2010-07-01

Applicant: Jeffrey G. Barrow

Inventor： Jeffrey G. Barrow

IPC: H03L5/00

CPC classification number: H03K3/356165

Abstract: Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal.

公开(公告)号：US08294249B2

公开(公告)日：2012-10-23

申请号：US12186447

申请日：2008-08-05

Applicant: David J. Pilling ,  Jitesh Shah ,  Diane Peng ,  Derek Huang

Inventor： David J. Pilling ,  Jitesh Shah ,  Diane Peng ,  Derek Huang

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L23/49503 ,  H01L23/49822 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20752

Abstract: A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.

Abstract translation: 公开了一种引线框架封装，其中传输信号通过不超过一根接合线的直径三倍的接合线从一对引线框架耦合到管芯中。 在一些实施例中，承载差分传输信号的引线框对可以被相邻的接地和电源引线屏蔽，所述接地和电源引线通过接合线耦合到管芯中，所述接合线也被分开不超过一个接合线的直径的三倍 。

公开(公告)号：US08284790B1

公开(公告)日：2012-10-09

申请号：US12701472

申请日：2010-02-05

Applicant: Raghunath Reddy Kommidi ,  David Alan Brown

Inventor： Raghunath Reddy Kommidi ,  David Alan Brown

IPC: H04L12/56

CPC classification number: H04L49/506 ,  H04L47/33 ,  H04L47/566 ,  H04L47/6205 ,  H04L49/3018 ,  H04L49/508

Abstract: A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.

Abstract translation: 分组交换机在入口端口接收分组，生成分组的入库记录，并将入库记录存储在入队结构中。 分组的入队记录包括用于指示允许通过规则是否适用于分组的通过标志。 分组交换机基于入队记录和包括允许通过规则的一组排序规则来确定存储在入口端口中的分组的路由顺序。 如果分组交换机中的分组被阻塞，则分组交换机基于入队记录和排序规则集来识别存储在入口端口中的最旧的未阻塞可路由分组。 此外，分组交换机通过分组交换机路由最旧的未阻塞可路由分组。 以这种方式，分组交换机允许最早的未阻塞可路由分组通过分组交换机中的阻塞分组。