公开(公告)号：US06846712B2

公开(公告)日：2005-01-25

申请号：US10440508

申请日：2003-05-16

申请人： Yi Ding

发明人： Yi Ding

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529

摘要： In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness. Portions of the control gates (170) overlie the select gates.

摘要翻译： 在非易失性存储器中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）同时形成。 在非易失性存储器中，用于外围晶体管的栅极电介质（130）和用于选择栅极（140）的栅极电介质（130）具有相同的厚度。 控制门（170）的一部分覆盖选择门。

公开(公告)号：US06838342B1

公开(公告)日：2005-01-04

申请号：US10678317

申请日：2003-10-03

申请人： Yi Ding

发明人： Yi Ding

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328

摘要： A floating gate of a nonvolatile memory cell is formed from two conductive layers (410.1, 410.2). A dielectric (210) in substrate isolation regions and the first of the two conductive layers providing the floating gates (410.1) are formed so that the dielectric has an exposed sidewall. At least the top portion of the sidewall is exposed. Then some of the dielectric is removed from the exposed portions of the dielectric sidewalls to laterally recess the sidewalls. Then the second conductive layer (410.2) for the floating gates is formed. The recessed sidewalls of the dielectric allow the second conductive layer to expand laterally, thus increasing the capacitive coupling between the floating and control gates and improving the gate coupling ratio.

摘要翻译： 非易失性存储单元的浮栅由两个导电层（410.1,410.2）形成。 形成衬底隔离区域中的电介质（210）和提供浮置栅极（410.1）的两个导电层中的第一个，使得电介质具有暴露的侧壁。 至少暴露侧壁的顶部。 然后从电介质侧壁的暴露部分去除一些电介质以横向凹入侧壁。 然后形成用于浮动栅极的第二导电层（410.2）。 介质的凹陷侧壁允许第二导电层横向膨胀，从而增加浮动栅极和控制栅极之间的电容耦合并提高栅极耦合比。

公开(公告)号：US20040209436A1

公开(公告)日：2004-10-21

申请号：US10681125

申请日：2003-10-09

申请人： ProMOS Technologies Inc.

发明人： Shih-Fang Chen

IPC分类号： H01L021/20

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.

摘要翻译： 用于防止寄生泄漏的沟槽电容器工艺。 该过程能够阻挡来自与沟槽相邻的寄生晶体管的漏电流，并且包括以下步骤：形成掺杂层和覆盖沟槽的侧壁部分的覆盖层，并对掺杂层执行退火处理以形成 掺杂剂区域，并且阻挡来自与沟槽相邻的寄生晶体管的泄漏电流。

公开(公告)号：US20040115948A1

公开(公告)日：2004-06-17

申请号：US10317039

申请日：2002-12-12

申请人： ProMOS Technologies, Inc.

发明人： Yung Hsien Wu ,  Jer Lee

IPC分类号： H01L021/302

CPC分类号： H01L21/02238 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3143

摘要： A method for manufacturing a semiconductor device that includes providing a first layer, cleaning the first layer, growing an oxide layer over the first layer at a reduced pressure from an atmospheric pressure, and depositing a nitride layer over the oxide layer, wherein the growing of the oxide layer and depositing of the nitride layer are performed in the same furnace.

摘要翻译： 一种制造半导体器件的方法，包括提供第一层，清洁第一层，在大气压力的减压下在第一层上生长氧化物层，以及在氧化物层上沉积氮化物层，其中生长 氧化物层和氮化物层的沉积在相同的炉中进行。

公开(公告)号：US20030139038A1

公开(公告)日：2003-07-24

申请号：US10138104

申请日：2002-05-03

申请人： ProMos Technologies, Inc.

发明人： S.C. Sun

IPC分类号： H01L021/4763 ,  H01L021/44

CPC分类号： H01L21/823842 ,  H01L21/823835

摘要： A method for manufacturing a semiconductor element is provided. The method includes a first silicon region, a second silicon region, and a metal silicide layer, wherein the metal silicide layer contacts with the first silicon region and the second silicon region separately, the method including steps of performing a first doping process to dope an N-type dopant into the first silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the first silicon region, and performing a second doping process to dope a P-type dopant into the second silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the second silicon region.

摘要翻译： 提供一种半导体元件的制造方法。 该方法包括第一硅区域，第二硅区域和金属硅化物层，其中金属硅化物层分别与第一硅区域和第二硅区域接触，该方法包括以下步骤：执行第一掺杂工艺以掺杂 将N型掺杂剂注入到第一硅区域中，并且将扩散阻挡杂质掺杂到与第一硅区接触的金属硅化物层的一部分中，以及执行第二掺杂工艺以将P型掺杂剂掺杂到第二硅区域中， 以将扩散阻挡杂质掺杂到与第二硅区接触的金属硅化物层的一部分中。

公开(公告)号：US20030127738A1

公开(公告)日：2003-07-10

申请号：US10305147

申请日：2002-11-27

申请人： ProMOS Technologies Inc.

发明人： Brian S. Lee ,  John Walsh

IPC分类号： H01L023/52 ,  H01L027/01 ,  H01L021/4763

CPC分类号： H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76859 ,  H01L21/823871

摘要： The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1nullx (0

摘要翻译： 本发明提供一种半导体器件，其中通过使用SixGe1-x（0

公开(公告)号：US20030049935A1

公开(公告)日：2003-03-13

申请号：US10218626

申请日：2002-08-15

申请人： PROMOS TECHNOLOGIES INC.

发明人： Hou-Hong Chou ,  Jiun-Fang Wang

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： B08B1/04 ,  B08B3/08 ,  H01L21/02052 ,  H01L21/31053 ,  H01L21/31105

摘要： The present invention provides a method of removing residual particles from a polished surface. The method comprises the steps of: providing a substrate, forming a dielectric layer on the substrate, brush-cleaning and etching the dielectric layer on the substrate with a liquid when residual particles are lodged therein, whereby the residual particles are loosened and then relocated to the dielectric layer, and finally cleaning the dielectric layer to remove the relocated residual particles.

摘要翻译： 本发明提供从抛光表面除去残留颗粒的方法。 该方法包括以下步骤：提供衬底，在衬底上形成电介质层，当剩余颗粒沉积在其中时，用液体刷洗和蚀刻衬底上的电介质层，由此残留的颗粒松动然后重新定位到 介电层，最后清洁电介质层以除去重新定位的残留颗粒。

公开(公告)号：US20030022486A1

公开(公告)日：2003-01-30

申请号：US10097052

申请日：2002-03-13

申请人： ProMOS Technologies Inc.

发明人： Joseph Wu

IPC分类号： H01L021/44 ,  H01L021/4763

CPC分类号： H01L21/76804 ,  H01L21/76877

摘要： The present invention provides a method to prevent short of contact and metal lines. The method is applied in a substrate formed with a number of contact windows. The method is comprised of: (a) forming a first conductive layer in the contact windows without filling up the contact windows; (b) forming liners in the contact windows to reduce the openings of the contact windows; (c) forming liner trenches in the contact windows; and (d) forming a second conduction layer on top of the first conductive layer in the contact windows. According to this invention, shorts between contact windows and metal lines is effectively prevented. Therefore, the product yield is greatly improved.

摘要翻译： 本发明提供一种防止接触不良和金属线的方法。 该方法应用于形成有多个接触窗口的基板中。 该方法包括：（a）在接触窗口中形成第一导电层而不填充接触窗口; （b）在接触窗中形成衬垫以减少接触窗的开口; （c）在接触窗中形成衬垫槽; 和（d）在接触窗口中的第一导电层的顶部上形成第二导电层。 根据本发明，有效地防止了接触窗和金属线之间的短路。 因此，产品产量大大提高。

公开(公告)号：US6130155A

公开(公告)日：2000-10-10

申请号：US347171

申请日：1999-07-02

申请人： Jeng-Pei Chen ,  Chung-Yi Chiu ,  Chang Hsun Lee

发明人： Jeng-Pei Chen ,  Chung-Yi Chiu ,  Chang Hsun Lee

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02071 ,  H01L21/32139 ,  H01L21/76888 ,  H01L21/0276

摘要： A method of forming metal lines is disclosed. The method comprises the steps of: forming a composite metal layer over a wafer, the composite metal layer having a top layer of titanium/titanium nitride; oxidizing the top layer of titanium/titanium nitride to form a layer of titanium oxide; and patterning and etching the composite metal layer to form the metal lines.

摘要翻译： 公开了一种形成金属线的方法。 该方法包括以下步骤：在晶片上形成复合金属层，所述复合金属层具有顶层钛/氮化钛; 氧化钛/氮化钛的顶层以形成一层氧化钛; 以及图案化和蚀刻复合金属层以形成金属线。

公开(公告)号：US6007405A

公开(公告)日：1999-12-28

申请号：US118171

申请日：1998-07-17

申请人： Len Mei

发明人： Len Mei

IPC分类号： B24B37/013 ,  B24B49/04 ,  B24B49/10 ,  B24B249/00

CPC分类号： B24B37/013 ,  B24B49/04 ,  B24B49/10

摘要： A chemical mechanical polisher for polishing a surface of a semiconductor wafer is disclosed. The polisher comprises: a polishing table for holding a polishing pad; a rotatable wafer chuck for holding said semiconductor wafer against said polishing pad; an electrical lapping guide secured to said wafer chuck, said electrical lapping guide comprising: a polishable resistive sensor that has a variable resistance dependent upon the amount of material removed from said resistive sensor during polishing; and a bias means for applying a bias to said resistive sensor such that said resistive sensor is in contact with said polishing pad during polishing; a resistance sensing means for determining said variable resistance of said resistive sensor; and a microprocessor for determining the amount of material polished from said resistive sensor based upon said variable resistance.

摘要翻译： 公开了一种用于抛光半导体晶片表面的化学机械抛光机。 抛光机包括：用于保持抛光垫的抛光台; 用于将所述半导体晶片保持在所述抛光垫上的可旋转晶片卡盘; 所述电研磨引导件包括：可抛光电阻传感器，其具有取决于在抛光期间从所述电阻传感器去除的材料量的可变电阻; 以及用于向所述电阻式传感器施加偏压使得所述电阻式传感器在抛光期间与所述抛光垫接触的偏压装置; 用于确定所述电阻式传感器的所述可变电阻的电阻感测装置; 以及微处理器，用于基于所述可变电阻来确定从所述电阻式传感器抛光的材料的量。