公开(公告)号：US20050064606A1

公开(公告)日：2005-03-24

申请号：US10902508

申请日：2004-07-29

Applicant: Fabio Pellizzer ,  Roberto Bez

Inventor： Fabio Pellizzer ,  Roberto Bez

IPC: H01L27/24 ,  H01L21/00

CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract translation: 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。

公开(公告)号：US20050063589A1

公开(公告)日：2005-03-24

申请号：US10937808

申请日：2004-09-09

Applicant: Riccardo Angrilli ,  Renzo Arce Arguedas ,  Eros Pedrini ,  Andrea Marchi

Inventor： Riccardo Angrilli ,  Renzo Arce Arguedas ,  Eros Pedrini ,  Andrea Marchi

IPC: G06F12/00 ,  G06K9/34 ,  G06T1/60 ,  G06T5/00

CPC classification number: G06T7/12 ,  G06T2200/28 ,  G06T2207/10016 ,  G06T2207/30252

Abstract: A method for extracting a subset of data from an ordered set of bi-dimensional matrices (data arrays) such as a sequence of pictures or a multi-dimensional matrix, for instance, is implemented by dedicated hardware that may be used each time it is necessary to extract a subset of data from a data array. For each matrix of data, the method calculates very quickly row and column indices of border data of the portion to be extracted, which are obtained by arithmetical operations among row and column indices of vertices of a closed area of interest. The method is implemented in a device for selectively transferring a data stream sampled at a certain bit-rate to a microprocessor unit or to a memory receiving the data stream at a different rate.

Abstract translation: 例如，从例如图片序列或多维矩阵的二维矩阵（数据阵列）的有序集合中提取数据的子集的方法由专用硬件实现，每当它们被 必须从数据数组中提取数据子集。 对于每个数据矩阵，该方法非常快速地计算要提取部分的边界数据的行和列索引，这些索引是通过关闭区域的顶点的行和列索引之间的算术运算获得的。 该方法在用于选择性地将以某一比特率采样的数据流传送到微处理器单元或以不同速率接收数据流的存储器的设备中实现。

公开(公告)号：US20050057309A1

公开(公告)日：2005-03-17

申请号：US10942617

申请日：2004-09-16

Applicant: Giuseppe Gramegna

Inventor： Giuseppe Gramegna

IPC: H03F1/08 ,  H03F1/32 ,  H03F3/45 ,  H03F1/14

CPC classification number: H03F3/45085 ,  H03F1/083 ,  H03F1/3211 ,  H03F2200/294 ,  H03F2200/372

Abstract: An amplifier includes at least a first transistor which has a first input signal at a first input terminal and has a first output terminal at which a first output amplified signal is present. The first transistor comprises a first parasitic capacitive element which is arranged between the first input and output terminals and through which a first current flows. The stagecomprises a device having a second output terminal with an output signal having a value equal to but of different sign from the first output signal and it comprises at least one element which is arranged between the first input terminal of the first transistor and the second output terminal of the device and which is passed through by a second current having a value equal to but of different sign from the first current.

Abstract translation: 放大器至少包括第一晶体管，其在第一输入端具有第一输入信号，并具有第一输出端，​​第一输出端存在第一输出放大信号。 第一晶体管包括布置在第一输入和输出端之间的第一寄生电容元件，第一电流流过第一寄生电容元件。 该装置具有具有第二输出端子的装置，其输出信号的值等于但不同于第一输出信号的符号，并且它包括布置在第一晶体管的第一输入端和第二输出端之间的至少一个元件 终端，并且其具有与第一电流具有等于但不同符号的值的第二电流通过。

公开(公告)号：US20050040977A1

公开(公告)日：2005-02-24

申请号：US10861340

申请日：2004-06-04

Applicant: Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

Inventor： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

IPC: G11C7/14 ,  G11C16/28 ,  H03M1/10

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract translation: 描述了一种用于产生连接到存储器矩阵的单元的读出放大器的参考电流的方法，包括以下步骤：通过参考单元产生第一参考电流模拟信号，执行第一模拟信号的模数转换为 参考电流数字信号，将连接线上的数字信号发送到感测放大器，并且将数字信号进行数模转换成第二参考电流模拟信号，以作为参考电流施加到感测放大器。

公开(公告)号：US20050035468A1

公开(公告)日：2005-02-17

申请号：US10864901

申请日：2004-06-09

Applicant: Antonio Andreini ,  Lorenzo Cerati ,  Paola Galbiati ,  Alessandra Merlini

Inventor： Antonio Andreini ,  Lorenzo Cerati ,  Paola Galbiati ,  Alessandra Merlini

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.

Abstract translation: 描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述 信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。

公开(公告)号：US20050018923A1

公开(公告)日：2005-01-27

申请号：US10848815

申请日：2004-05-18

Applicant: Giuseppe Messina ,  Sebastiano Battiato ,  Alfio Castorina ,  Laurent Plaza

Inventor： Giuseppe Messina ,  Sebastiano Battiato ,  Alfio Castorina ,  Laurent Plaza

IPC: H04N9/64 ,  G06K9/00 ,  G06T5/40 ,  H04N1/407 ,  H04N1/46 ,  H04N1/60 ,  G06K9/40

CPC classification number: G06T5/007 ,  G06K9/00234 ,  G06T5/40 ,  H04N1/6027

Abstract: A digital image processing method includes extracting chromatic information of an image taken by an image taking device and related to a human subject; detecting visually interesting regions; and exposure correcting of the taken image by normalizing a grey scale of the taken image based on the visually interesting regions. Advantageously, the method includes recognizing areas corresponding to the skin of the subject, these areas being used as the visually interesting regions for the exposure correction step.

Abstract translation: 一种数字图像处理方法，包括提取由摄像装置拍摄并与人类对象相关的图像的色彩信息; 检测视觉上有趣的区域; 以及通过基于视觉上有趣的区域归一化所拍摄图像的灰度来对拍摄图像进行曝光校正。 有利地，该方法包括识别与对象的皮肤相对应的区域，这些区域被用作用于曝光校正步骤的视觉上有趣的区域。

公开(公告)号：US20040235149A1

公开(公告)日：2004-11-25

申请号：US10874902

申请日：2004-06-23

Applicant: STMicroelectronics S.r.I.

Inventor： Gabriele Barlocchi ,  Flavio Villa

IPC: C12M001/34

CPC classification number: B01L7/52 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0825 ,  B01L2300/1827 ,  B01L2300/1883

Abstract: Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Abstract translation: 集成的微反应器，形成在一体的整体中并且包括半导体材料区域和绝缘层; 在半导体材料区域中延伸的掩埋沟道; 在所述半导体材料区域和所述绝缘层中延伸并与所述掩埋沟道连通的第一和第二访问沟槽; 第一和第二储存器，其形成在所述绝缘层的顶部上并且与所述第一和第二接入沟槽连通; 由绝缘层形成的悬浮膜，横向于埋设通道; 以及由悬挂隔膜支撑的检测电极，在绝缘层上方和第二储存器内部。

公开(公告)号：US20040223616A1

公开(公告)日：2004-11-11

申请号：US10818695

申请日：2004-04-06

Applicant: STMicroelectronics S.r.I.

Inventor： Ljupco Kocarev ,  Zarko Tasev ,  Paolo Amato ,  Gianguido Rizzotto

IPC: H04L009/00

CPC classification number: H04L9/001 ,  H04L9/3013 ,  H04L9/302 ,  H04L9/3093

Abstract: An encryption process includes choosing a secret key and a set of permutable functions defined on a phase space for encrypting/decrypting messages, choosing a code for encoding messages to be sent as a number belonging to the phase space. The set of permutable functions includes chaotic maps generated by a composite function of first and second functions, and an inverse of the first function. The secret key is defined by the second function.

Abstract translation: 加密过程包括：选择用于对消息进行加密/解密的相位空间上定义的秘密密钥和一组置换函数，选择用于编码要作为属于相位空间的数字发送的消息的代码。 可置换函数的集合包括由第一和第二函数的复合函数产生的混沌映射，以及第一函数的逆。 秘密密钥由第二个功能定义。

公开(公告)号：US20040223361A1

公开(公告)日：2004-11-11

申请号：US10779856

申请日：2004-02-17

Applicant: STMicroelectronics S.r.I.

Inventor： Antonino La Malfa ,  Marco Messina

IPC: G11C011/00

CPC classification number: G11C16/12

Abstract: Described herein is a method for soft-programming an electrically erasable nonvolatile memory device, wherein soft-programming is carried out with a soft-programming multiplicity equal to twice that used for writing data in the memory device until the current absorbed during soft-programming is smaller than or equal to the maximum current which is available for writing operations and which can be generated within the memory device, and with a soft-programming multiplicity equal to the one used for writing data in the memory device in the case where the current absorbed during soft-programming with double multiplicity is greater than the maximum current which is available for writing operations and which can be generated within the memory device.

Abstract translation: 这里描述了一种用于软编程电可擦除非易失性存储器件的方法，其中以软编程多重性等于用于在存储器件中写入数据的两倍的软编程来执行软编程，直到在软编程期间吸收的电流为 小于或等于可用于写入操作并且可以在存储器件内产生的最大电流，并且在电流吸收的情况下具有与用于在存储器件中写入数据的软编程多重性相等的软编程倍数 在具有双重多重性的软编程期间，大于可用于写入操作的最大电流，并且可以在存储器件内生成。

公开(公告)号：US20040156235A1

公开(公告)日：2004-08-12

申请号：US10719650

申请日：2003-11-21

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Bellini ,  Mauro Sali ,  Alessandro Magnavacca ,  Carlo Lisi

IPC: G11C011/34

CPC classification number: G11C16/26 ,  G11C16/344 ,  G11C2216/22

Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

Abstract translation: 具有同时读/写的非易失性存储器件具有由组织到存储体中的多个单元形成的存储器阵列以及多个第一和第二读出放大器。 该装置还具有与相应的单元组相关联的多个R / W选择器，并将各组单元的单元交替地连接到第一读出放大器和第二读出放大器。