公开(公告)号：US20080240157A1

公开(公告)日：2008-10-02

申请号：US12056537

申请日：2008-03-27

Applicant: Takanobu Muraguchi ,  Fumio Sudo

Inventor： Takanobu Muraguchi ,  Fumio Sudo

IPC: H04J3/22

CPC classification number: H04L49/9047 ,  H04L49/90

Abstract: A received frame processing device that receives a frame of variable length from a network, and transfers the frame to a buffer group that is provided on a system memory and is a common area to a CPU, wherein a buffer includes a plurality of buffers. And a second frame is transferred to a first buffer when the second frame is received before a given amount of time has elapsed after a first frame has been transferred to the first buffer, on the other hand, the second frame is transferred to a second buffer after the ownership of the first buffer has been transferred to the CPU when the second frame is received after the first frame has been transferred to the first buffer and after a given amount of time or longer has elapsed.

Abstract translation: 一种接收到的帧处理装置，从网络接收可变长度的帧，并将帧传送到提供在系统存储器上的缓冲器组，并且是CPU的公共区域，其中缓冲器包括多个缓冲器。 并且当在第一帧已被传送到第一缓冲器之前经过一段给定的时间量之前第二帧被接收时，第二帧被传送到第一缓冲器，另一方面，第二帧被传送到第二缓冲器 在第一帧已经被传送到第一缓冲器之后以及经过给定的时间或更长时间之后，当接收到第二帧时，将第一缓冲器的所有权转移到CPU之后。

公开(公告)号：US20080239949A1

公开(公告)日：2008-10-02

申请号：US12054867

申请日：2008-03-25

Applicant: HIDEKI NISHIZAKI

Inventor： HIDEKI NISHIZAKI

IPC: H04L12/26 ,  H04L12/28 ,  H04L12/56

CPC classification number: H04L12/5601 ,  H04L47/125 ,  H04L49/1515 ,  H04L49/1576 ,  H04L49/3027 ,  H04L49/3081 ,  H04L49/508 ,  H04L49/552 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

Abstract: In cell read from a buffer for each priority provided in the intermediate stage buffers 1-5-1-1-5-N, cells can be read even from a low priority buffer within a fixed time period and at the output interfaces 1-12-1-1-12-N, cell arrival can be monitored individually on a priority basis and on a basis of each of the input interfaces 1-1-1-1-1-N while taking a cell reading cycle at the intermediate stage buffer into consideration.

Abstract translation: 在中间级缓冲器1-5-1-1N中提供的每个优先级的从缓冲器读取的单元中，甚至可以在固定时间段内的低优先级缓冲器和输出接口1-12处读取单元 可以在优先级基础上并且基于每个输入接口1-1-1-1 -N来单独监视小区到达，同时在中间阶段进行小区读取周期 缓冲考虑。

公开(公告)号：US07411969B2

公开(公告)日：2008-08-12

申请号：US10696425

申请日：2003-10-28

Applicant: Ling Cen

Inventor： Ling Cen

IPC: H04L12/56

CPC classification number: H04L47/35 ,  H04L47/16 ,  H04L47/39 ,  H04L47/50 ,  H04L47/522 ,  H04L47/6205 ,  H04L47/621 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

Abstract: A system, apparatus, and method for a link layer protocol to utilize a main buffer and share the remaining link units according to a list buffer or FIFO. The system includes an efficient link layer to facilitate transmitting and receiving data and information. The list buffer is used to store the buffer indexes for all the link units for the respective virtual connections.

Abstract translation: 一种用于链路层协议的系统，装置和方法，其利用主缓冲器并根据列表缓冲器或FIFO共享剩余的链路单元。 该系统包括有效的链路层，以便于发送和接收数据和信息。 列表缓冲区用于存储各个虚拟连接的所有链路单元的缓冲区索引。

公开(公告)号：US07411957B2

公开(公告)日：2008-08-12

申请号：US10811195

申请日：2004-03-26

Applicant: John Kenneth Stacy ,  Trevor Garner ,  Martin W. Hughes ,  William R. Lee

Inventor： John Kenneth Stacy ,  Trevor Garner ,  Martin W. Hughes ,  William R. Lee

IPC: H04L12/28 ,  G06F11/30

CPC classification number: H04L49/901 ,  H04L47/32 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9047 ,  H04L63/1416 ,  H04L63/1458

Abstract: A system and method is provided for automatically identifying and removing malicious data packets, such as denial-of-service (DoS) packets, in an intermediate network node before the packets can be forwarded to a central processing unit (CPU) in the node. The CPU's processing bandwidth is therefore not consumed identifying and removing the malicious packets from the system memory. As such, processing of the malicious packets is essentially “off-loaded” from the CPU, thereby enabling the CPU to process non-malicious packets in a more efficient manner. Unlike prior implementations, the invention identifies malicious packets having complex encapsulations that can not be identified using traditional techniques, such as ternary content addressable memories (TCAM) or lookup tables.

Abstract translation: 提供了一种系统和方法，用于在分组可以转发到节点中的中央处理单元（CPU）之前自动识别和去除中间网络节点中的恶意数据分组，例如拒绝服务（DoS）分组。 因此，CPU的处理带宽不被识别并从系统内存中删除恶意数据包。 因此，恶意数据包的处理本质上从CPU中“卸载”，从而使CPU能够以更有效的方式处理非恶意数据包。 与先前的实现不同，本发明识别具有复杂封装的恶意数据包，这些封装不能使用诸如三进制内容可寻址存储器（TCAM）或查找表之类的传统技术来识别。

公开(公告)号：US20080183884A1

公开(公告)日：2008-07-31

申请号：US11952897

申请日：2007-12-07

Applicant: Wei-Pin Chen ,  Edward Ku ,  Yun-Fei Chao

Inventor： Wei-Pin Chen ,  Edward Ku ,  Yun-Fei Chao

IPC: G06F15/16

CPC classification number: H04L49/9047 ,  H04L29/06 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/32 ,  H04L49/3018 ,  H04L49/505 ,  H04L49/90

Abstract: A data-packet processing method is used in a network system. The network system includes a buffer for optionally storing a data packet to be transferred, and the method includes steps of: determining a type of the data packet to be transferred; determining a storage state of a buffer where the data packet is to be temporarily stored before transferring; and storing the data packet into the buffer if the storage state of the buffer is a packet-accepting storage state; wherein the packet-accepting storage state of the buffer varies with the type of the data packet.

Abstract translation: 在网络系统中使用数据包处理方法。 网络系统包括用于可选地存储要传送的数据分组的缓冲器，并且该方法包括以下步骤：确定要传送的数据分组的类型; 在传送之前确定要临时存储数据分组的缓冲器的存储状态; 以及如果所述缓冲器的存储状态是分组接受存储状态，则将所述数据分组存储到所述缓冲器中; 其中缓冲器的分组接受存储状态随数据分组的类型而变化。

公开(公告)号：US07403976B2

公开(公告)日：2008-07-22

申请号：US11323814

申请日：2005-12-29

Applicant: David A. Brown

Inventor： David A. Brown

IPC: G06F15/167

CPC classification number: H04L47/30 ,  H04L47/70 ,  H04L49/103 ,  H04L49/201 ,  H04L49/252 ,  H04L49/9047

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

Abstract translation: 交换机在共享存储器中包括一个保留的缓冲区池。 保留的缓冲池被保留供出口端口独占使用。 该交换机包括池选择逻辑，其从保留池中选择一个空闲缓冲区，用于存储从入口端口接收的数据以转发到出口端口。 共享内存还包括一个共享的缓冲池。 共享缓冲区池由多个出口端口共享。 池选择逻辑在检测到预留池中没有可用缓冲区时，会选择共享池中的空闲缓冲区。 共享存储器还可以包括缓冲器的多播池。 缓冲区的组播池由多个出口端口共享。 池选择逻辑在检测到从入口端口接收到的IP组播数据包时，选择多播池中的空闲缓冲区。

公开(公告)号：US20080107138A1

公开(公告)日：2008-05-08

申请号：US11739491

申请日：2007-04-24

Applicant: Ching-Yih Tseng ,  Yu-Chi Chen

Inventor： Ching-Yih Tseng ,  Yu-Chi Chen

IPC: H04J3/12

CPC classification number: H04L49/9094 ,  H04L5/04 ,  H04L25/0204 ,  H04L49/90 ,  H04L49/9047

Abstract: An apparatus and method for a receiver to recognize channel numbers, skew delays, and polarities of N channels by extracting the properties of the transmitted signals are provided. Each of the N signals comprises a plurality of digital symbols with certain characteristics known to the receiver. The apparatus comprises a calculation unit, a statistic unit, and a selection unit. The calculation unit is used to compute a value for each channel according to the properties of the digital symbols captured on that particular channel within a predetermined interval. The statistic unit is used to derive a plurality of statistical values based on the values from the calculation unit. The selection unit recognizes the special property of a channel, identifies the remaining N−1 channels, compensates the skew delays, and corrects polarities.

Abstract translation: 提供了一种用于通过提取发送信号的属性来识别N个信道的信道号，偏差延迟和极性的接收机的装置和方法。 N个信号中的每一个包括具有接收机已知的某些特性的多个数字符号。 该装置包括计算单元，统计单元和选择单元。 计算单元用于根据在预定间隔内在该特定信道上捕获的数字符号的属性来计算每个信道的值。 统计单元用于基于来自计算单元的值导出多个统计值。 选择单元识别通道的特殊属性，识别剩余的N-1个通道，补偿偏斜延迟并校正极性。

公开(公告)号：US20080056278A1

公开(公告)日：2008-03-06

申请号：US11976862

申请日：2007-10-29

Applicant: Shiri Kadambi ,  Shekhar Ambe

Inventor： Shiri Kadambi ,  Shekhar Ambe

IPC: H04L12/56

CPC classification number: H04L12/46 ,  H04L12/18 ,  H04L12/42 ,  H04L12/4625 ,  H04L12/4641 ,  H04L12/4645 ,  H04L12/467 ,  H04L12/56 ,  H04L12/5602 ,  H04L45/24 ,  H04L45/245 ,  H04L45/54 ,  H04L45/742 ,  H04L47/10 ,  H04L47/125 ,  H04L47/15 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/286 ,  H04L47/50 ,  H04L47/6215 ,  H04L47/6225 ,  H04L47/623 ,  H04L49/102 ,  H04L49/109 ,  H04L49/201 ,  H04L49/208 ,  H04L49/254 ,  H04L49/3054 ,  H04L49/3081 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/45 ,  H04L49/602 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9057 ,  H04L49/9073 ,  H04L67/10 ,  H04L69/14 ,  H04L69/16 ,  H04L69/161

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Abstract translation: 用于网络通信的网络交换机包括第一数据端口接口，其中第一数据端口接口支持用于以第一数据速率发送和接收数据的多个数据端口。 网络交换机还包括第二数据端口接口，其中第二数据端口接口支持用于以第二数据速率发送和接收数据的多个数据端口，以及用于在第三数据发送和接收数据的第三数据端口接口 率。 提供并配置CPU接口与CPU进行通信。 交换机包括与第一，第二和第三数据端口接口通信的第一，第二和第三内部存储器。 还提供了用于传送数据并控制与第二内部存储器的访问的第一和第二存储器管理单元。 提供用于传送数据和消息传递信息的通信信道。

公开(公告)号：US07337253B2

公开(公告)日：2008-02-26

申请号：US11386323

申请日：2006-03-22

Applicant: Christian D. Kasper

Inventor： Christian D. Kasper

IPC: G06F13/24 ,  H04L12/56 ,  H04L12/28 ,  G06F13/368

CPC classification number: H04L49/9021 ,  H04L49/103 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9047 ,  H04L49/9063 ,  H04L49/9068

Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

Abstract translation: 公开了一种用于路由布置在帧中的基于网络的数据的方法和系统。 主机处理器分析传输的数据突发，并发起一个地址和查找算法，用于将帧发送到所需的目的地。 存在于与主处理器结合工作的网络设备（例如，HDLC控制器）之间的共享系统存储器接收包括任何预先选择的地址字段的数据。 网络设备包括多个端口。 每个端口包括用于接收帧的至少第一部分的FIFO接收存储器。 帧的第一部分包括具有预选地址字段的数据。 直接存储器访问单元将数据从FIFO接收存储器传送到共享系统存储器。 通信处理器基于要由主处理器分析的期望的地址字段来选择要从FIFO接收存储器传送的数据量。

公开(公告)号：US07336674B2

公开(公告)日：2008-02-26

申请号：US10701793

申请日：2003-11-05

Applicant: Eitan Medina ,  Rami Rozenzveig ,  David Shemla

Inventor： Eitan Medina ,  Rami Rozenzveig ,  David Shemla

IPC: G06F15/16 ,  H04L12/56

CPC classification number: H04L49/103 ,  G06F15/17375 ,  H04L49/201 ,  H04L49/30 ,  H04L49/501 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract translation: 提供了一种用于管理分组存储器的方法和装置。 该装置包括空列表，存储缓冲器和用于更新存储缓冲器和空列表的装置。 空列表包括多个单个位缓冲区。 存储缓冲器包括多个连续缓冲器，其中每个单个位缓冲器与一个连续缓冲器相关联。 单个位缓冲器的位的状态指示相关连续缓冲器的空或完全状态，连续缓冲器的地址是其相关联的单位缓冲器的地址或编号的简单函数。 更新装置将数据存储在相邻缓冲器中并从其中移除数据，并相应地更新相关联的单个位缓冲器的状态。