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156 条记录 (耗时 0.031 秒)

    Fixed clock based arbitrary symbol rate timing recovery loop
    83.
    发明授权
    Fixed clock based arbitrary symbol rate timing recovery loop 失效
    基于固定时钟的任意符号速率定时恢复循环

    公开(公告)号：US06295325B1

    公开(公告)日：2001-09-25

    申请号：US09114949

    申请日：1998-07-14

    申请人： Cecil William Farrow ,  Daniel J. Udovic ,  Vahid Marandi ,  Mohammad Shafiul Mobin ,  Kaylan Mondal ,  Kai-Chuen Wong

    发明人： Cecil William Farrow ,  Daniel J. Udovic ,  Vahid Marandi ,  Mohammad Shafiul Mobin ,  Kaylan Mondal ,  Kai-Chuen Wong

    IPC分类号： H03D318

    CPC分类号： H04L7/0278 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029

    摘要： A QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal. The continuously variable digital rate interpolators/decimators are configured at startup so as to produce output streams at the same programmed rational rate multiple of the nominal baud rate of the anticipated received data signal, assuming the fs sample timing offset adjustment stream provided by the timing recovery feedback element to be identically 0. The “nominal” fixed sampling rate fs of the received analog input signal need not be rationally related to the nominal baud rate of the anticipated received data signal.

    摘要翻译： QAM数据信号定时恢复环路反馈元件提供对两个连续可变数字速率内插器/抽取器的固定采样时间偏移调整，以按接收数据信号的实际波特率的编程有理速率倍数产生正交输出流。 假设由定时恢复提供的fs采样定时偏移调整流，启动时配置连续可变数字速率内插器/抽取器，以便产生与预期接收数据信号的额定波特率相同的编程有理数倍的输出流 反馈元件相同为0.接收的模拟输入信号的“额定”固定采样率fs不需要与预期接收数据信号的标称波特率合理相关。

    Processor powerdown operation using intermittent bursts of instruction clock
    84.
    发明授权
    Processor powerdown operation using intermittent bursts of instruction clock 有权
    处理器断电操作使用间歇性突发的指令时钟

    公开(公告)号：US06275948B1

    公开(公告)日：2001-08-14

    申请号：US09141511

    申请日：1998-08-27

    申请人： Laurence E. Bays ,  Jalil Fadavi-Ardekani ,  Kenneth Daniel Fitch ,  Richard Joseph Niescier

    发明人： Laurence E. Bays ,  Jalil Fadavi-Ardekani ,  Kenneth Daniel Fitch ,  Richard Joseph Niescier

    IPC分类号： G06F126

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F11/349 ,  G06F12/0646 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0278 ,  Y02D10/128 ,  Y02D10/34

    摘要： An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

    摘要翻译： 根据本发明的原理，处于低功率模式的处理单元的指令时钟由突发模式控制信号限定。 突发模式控制信号被允许启动和停止相关处理单元的指令流。 在所公开的实施例中，主时钟信号被时钟控制电路限定，以向相关处理单元提供指令时钟信号的脉冲串。 为了操作突发指令周期控制单元，用户将突发长度预编程到寄存器中，以将指令周期的长度设置到相关处理单元。 计数器中的最大计数器值设置提供给相关处理单元的指令周期突发的周期。 只要计数器的当前值小于或等于预编程突发长度，突发控制信号允许时钟控制器将主时钟信号或其他相关时钟信号作为指令时钟信号传递到相关处理 单元。 低功率突发模式，因此功率节省可以根据突发长度和最大计数器值的组合值进行调整。

    Memory bank organization correlating distance with a memory map
    85.
    发明授权
    Memory bank organization correlating distance with a memory map 失效
    记忆库组织将距离与记忆图相关联

    公开(公告)号：US06226726B1

    公开(公告)日：2001-05-01

    申请号：US09075946

    申请日：1998-05-12

    申请人： Bahram G. Kermani ,  Vladimir Sindalovsky

    发明人： Bahram G. Kermani ,  Vladimir Sindalovsky

    IPC分类号： G06F1206

    CPC分类号： G06F12/0646 ,  G06F12/06 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0278

    摘要： Memory banks are assigned to the memory map of a common processor in an order corresponding to a physical characteristic of the respective memory bank, e.g., a physical distance to the processor and/or an electrical distance to the processor. In this way, the operating frequency of the processor can be increased beyond conventionally guaranteed limits at the expense of abandoning the farthest memory banks when not necessary for a particular application. Similarly, abandonment of the farther memory banks in accordance with the principles of the present invention allows operation of the processing system at higher temperatures and/or lower power voltages. In another embodiment of the present invention, wait states may be added to accesses to the farther memory banks such that the closest memory banks may be operated at the highest possible performance level, e.g., without any wait states. The performance of the individual memory banks may be monitored and a wait state table adjusted to adjust to environmental conditions such as temperature and/or power voltage.

    摘要翻译： 存储体被分配到公共​​处理器的存储器映射表中，其顺序与对应于存储器组的物理特性（例如到处理器的物理距离）和/或与处理器的电距离相对应。 以这种方式，处理器的工作频率可以超过常规保证的限制，以牺牲特定应用不需要的最远存储体为代价。 类似地，根据本发明的原理放弃更远的存储体允许处理系统在更高的温度和/或更低的电源电压下运行。 在本发明的另一个实施例中，等待状态可以被添加到对更远的存储体的访问，使得最接近的存储体可以以最高可能的性能级别操作，例如没有任何等待状态。 可以监视各个存储体的性能，并且调整等待状态表以适应诸如温度和/或功率电压的环境条件。

    System for extending the width of a data bus
    86.
    发明授权
    System for extending the width of a data bus 失效
    用于扩展数据总线宽度的系统

    公开(公告)号：US6122697A

    公开(公告)日：2000-09-19

    申请号：US100890

    申请日：1998-06-22

    申请人： David Lawson Potts

    发明人： David Lawson Potts

    IPC分类号： G06F12/06 ,  G06F13/40 ,  H04L7/00 ,  H04L7/02 ,  G06F13/38

    CPC分类号： G06F13/4018 ,  G06F12/0646 ,  H04L7/0278 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029

    摘要： One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g., by a write to a write direction extra bits register addressable through a specific input/output (I/O) location. The extra bits are tacked on to a subsequent write cycle in the digital serial interface, e.g., in the AC '97 link, to write an excess length data word.

    摘要翻译： 本发明的一个方面提供一种用于数字串行接口的封隔器解包器（PUP），其允许多个处理器访问与数字串行接口有关的串行数据流的时隙寄存器。 配置寄存器由多个处理器中的一个处理器或每个处理器维护以仲裁对各个时隙寄存器的访问。 本发明的另一方面允许一个或多个处理器有效地访问和/或写入诸如时隙寄存器的资源，而不是处理器相应的数据总线允许的宽度。 为读写方向数据总线中的至少一个维持额外位寄存器。 额外的比特对应于从一个宽度的数据总线改变到较窄宽度的数据总线时常常被忽略的最低有效位。 写入方向上的额外位可通过例如通过写特定输入/输出（I / O）位置写入写入方向额外位寄存器来访问。 数字串行接口中的额外位被固定到例如AC '97链路中的后续写周期以写入超长数据字。

    Carrier independent timing recovery system for a vestigial sideband modulated signal
    88.
    发明授权
    Carrier independent timing recovery system for a vestigial sideband modulated signal 失效
    载波独立定时恢复系统，用于残留边带调制信号

    公开(公告)号：US5805242A

    公开(公告)日：1998-09-08

    申请号：US704787

    申请日：1996-09-06

    申请人： Christopher Hugh Strolle ,  Steven Todd Jaffe

    发明人： Christopher Hugh Strolle ,  Steven Todd Jaffe

    IPC分类号： H03D1/22 ,  H03D1/24 ,  H04L25/03 ,  H04L25/06 ,  H04L27/02 ,  H04L27/06 ,  H04N5/21 ,  H04N5/44 ,  H04N5/455 ,  H04L27/16

    CPC分类号： H04L7/0278 ,  H03D1/24 ,  H04L25/0305 ,  H04L25/0307 ,  H04L25/061 ,  H04L25/067 ,  H04L27/02 ,  H04L27/066 ,  H04N21/4382 ,  H04N5/211 ,  H04N5/455 ,  H03D1/2254 ,  H04L2025/03382 ,  H04L2025/0363 ,  H04N5/4401

    摘要： A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (.DELTA.) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal. A subsequent equalizer eliminates any residual phase offsets in the recovered signal.

    摘要翻译： PCT No.PCT / US95 / 03131 Sec。 371日期1996年9月6日 102（e）1996年9月6日PCT PCT 1995年3月13日PCT公布。 公开号WO95 / 26074 日期1995年9月28日用于处理以残留边带（VSB）格式发送的HDTV信号的电视信号接收机包括由定时恢复网络（30）和载波恢复网络（50）共享的输入复合滤波器。 滤波器网络包括一对在VSB信号的上和下边缘边缘成像的上下边缘滤波器（20,22），用于产生抑制的副载波AM输出信号。 定时恢复网络包括相位检测器（28,38,62），并响应从两个滤波器（经由26）得到的用于同步系统时钟（CLK）的AM信号。 载波恢复网络（50）还包括相位检测器（54,60,62,64），并对来自一个或两个滤波器的输出进行响应，以产生表示相位/频率偏移的输出误差信号（DELTA） VSB信号。 误差信号用于减少或消除偏移以产生恢复的基带或近基带信号。 随后的均衡器消除了恢复信号中的任何残留相位偏移。

    Timing control for Modem receivers
    90.
    发明授权
    Timing control for Modem receivers 失效
    调制解调器接收器的定时控制

    公开(公告)号：US4969163A

    公开(公告)日：1990-11-06

    申请号：US401896

    申请日：1989-09-01

    申请人： Gottfried Ungerboeck

    发明人： Gottfried Ungerboeck

    IPC分类号： H04L27/22 ,  H04L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L7/10

    CPC分类号： H04L7/0334 ,  H04L7/0278 ,  H04L7/10

    摘要： For a modem receiver using an adaptive equalizer with fractional tap spacing, method and apparatus are disclosed for controlling the sample-timing phase. By evaluating bandedge components of the received signal in a particular way, a timing-phase vector signal is derived which is independent of the signal energy at the bandedges and of the quality of frequency separation of the filters for the bandedge signals. After an initial period, the current timing-phase vector signal is captured and stored as a reference. Thereafter, the sampling phase of the receiver is kept at its initial random value, represented by the stored reference timing-phase vector. The necessity to initially change the sampling phase in the receiver to a value which is forced by the received signal is avoided.