公开(公告)号：US06842130B2

公开(公告)日：2005-01-11

申请号：US10812975

申请日：2004-03-31

Applicant: Minsheng Wang ,  Anil Tammineedi

Inventor： Minsheng Wang ,  Anil Tammineedi

IPC: G06F7/76 ,  H03M1/06 ,  H03M3/04 ,  H03M3/00

CPC classification number: G06F7/762 ,  H03M1/0665 ,  H03M3/338 ,  H03M3/464 ,  H03M3/502

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract translation: 用于混洗输入比特的数据洗牌装置包括多个比特洗牌器，每个比特混洗器输入相应的输入比特的两个比特x0和x1，并输出一个向量{x0'，x1'}，使得随着时间的推移，比特x0' 在位x1'的1的1'内。 至少两个4位向量混洗器输入向量{x0'，x1'}和输出4位向量，每个4位向量对应于由位产生的对应的两个向量{x0'，x1'}的组合 使得4位向量混洗器以与位混合器对位x0和x1进行操作相同的方式对矢量{x0'，x1'}进行操作。 基于4位向量洗牌器的下一个状态来更新位洗牌器的当前状态。

公开(公告)号：US6411980B2

公开(公告)日：2002-06-25

申请号：US77471301

申请日：2001-02-01

Applicant: TOSHIBA KK

Inventor： YOSHIDA TAKESHI

IPC: G06F5/01 ,  G06F7/50 ,  G06F7/76

CPC classification number: G06F7/507 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/764 ,  G06F2207/382 ,  G06F2207/3828

Abstract: Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask signal based on an amount of shift and split mode information. An output selector replaces data shifted by the shifter with code extension data bit by bit based on the mask signal, and outputs data which are shifted and code-extended according to the split mode information and arithmetic/logical shift information. In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an arithmetic result, which is obtained when no carry is supplied from lower digits, regardless of the carry from the lower digits.

Abstract translation: 并行地并行地进行输入数据的移位而不用移位器进行分割，代码扩展数据生成器的代码扩展数据的生成以及掩模信号发生器的掩蔽信号的生成。 屏蔽信号发生器基于移位量和分割模式信息产生屏蔽信号。 输出选择器基于掩码信号逐位地替换由移位器移位的代码扩展数据，并且根据分离模式信息和算术/逻辑移位信息输出被移位和代码扩展的数据。 在作为另一实施例的进位选择型加法器/减法器中，如果要执行分割并行处理，则一对单位加法器/减法器执行对于从低位指示不提供进位的情况下执行的算术运算， 然后选择器选择算术结果，该算术结果是当从低位数字提供进位时获得的，而与低位数字的进位无关。

公开(公告)号：US6145077A

公开(公告)日：2000-11-07

申请号：US645897

申请日：1996-05-14

Applicant: Nathan Mackenzie Sidwell ,  Catherine Louise Barnaby

Inventor： Nathan Mackenzie Sidwell ,  Catherine Louise Barnaby

IPC: G06F9/305 ,  G06F7/76 ,  G06F9/30 ,  G06F9/308 ,  G06F9/315 ,  G06F9/38 ,  G06F7/00

CPC classification number: G06F7/76 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3885

Abstract: A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called "packed instructions". Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganized within a data string thereby minimizing loading and storing operations to memory.

Abstract translation: 公开了一种计算机和操作计算机的方法，其允许在执行所谓的“打包指令”的上下文中操纵数据值。 打包指令在打包操作数上执行。 打包操作数包括由多个子串组成的数据串，每个子串定义特定的数据值或对象。 本发明涉及一种重组指令，其允许在数据串中重新组织对象，从而最小化对存储器的加载和存储操作。

公开(公告)号：US6072808A

公开(公告)日：2000-06-06

申请号：US997501

申请日：1997-12-23

Applicant: Dennis M. O'Connor

Inventor： Dennis M. O'Connor

IPC: G06F7/76 ,  G11B20/10 ,  G11B20/12 ,  H04J3/16 ,  H04L29/04 ,  H04N7/173 ,  H04N21/21 ,  H04N21/23 ,  H04H1/04

CPC classification number: G06F7/76 ,  G11B20/10 ,  G11B20/12 ,  H04N21/21 ,  H04N21/23 ,  H04N7/17318

Abstract: A data segment is provided with minimal access latency. The data segment is divided into three or more portions and provided via two or more channels. Each of the channels carries a portion of the data segment, the portion of the data segment carried by each channel being less than the entire data segment. Each of the channels repeat over time. In one embodiment, the two or more channels are physical channels. In another embodiment, the two or more channels are logical channels which are time-multiplexed over a single physical channel.

Abstract translation: 为数据段提供最小的访问延迟。 数据段被分为三个或更多个部分，并通过两个或更多个通道提供。 每个信道承载数据段的一部分，每个信道承载的数据段的部分小于整个数据段。 每个频道随时间重复。 在一个实施例中，两个或更多个信道是物理信道。 在另一个实施例中，两个或更多个信道是在单个物理信道上被时分多路复用的逻辑信道。

公开(公告)号：US06055648A

公开(公告)日：2000-04-25

申请号：US975282

申请日：1997-11-20

Applicant: Takaki Tokuyama ,  Motohide Tamura

Inventor： Takaki Tokuyama ,  Motohide Tamura

IPC: G06F7/00 ,  G06F7/76 ,  G06F11/00 ,  G06Q10/10

CPC classification number: G06F11/00

Abstract: The floating point data stored in an arbitrary cell is processed on the basis of a particular formula (S401), if an error due to column truncation occurs in a result of computation (S402) then the all the floating point data is converted to the fixed point data (S405), and the error occurring due to the floating point data is recovered automatically thereby improving the convenience of the recovery process.

Abstract translation: 存储在任意单元中的浮点数据基于特定的公式进行处理（S401），如果在计算结果中发生由于列截断引起的错误（S402），则将所有浮点数据转换为固定 点数据（S405），并且自动恢复由浮点数据引起的错误，从而提高恢复处理的便利性。

公开(公告)号：US5961640A

公开(公告)日：1999-10-05

申请号：US838021

申请日：1997-04-22

Applicant: Peter Chambers ,  Scott Edward Harrow ,  David Evoy

Inventor： Peter Chambers ,  Scott Edward Harrow ,  David Evoy

IPC: G06F7/76 ,  G06F13/40 ,  G06F17/00

CPC classification number: G06F7/768 ,  G06F13/4013

Abstract: An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data. In one embodiment, a byte stream is generated over the output bus. Alternatively, dwords are sent over the output bus in proper endian domain format. Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet. The novel system is well suited to process arbitrarily sized data packets as well as data packets starting at arbitrary byte boundaries.

Abstract translation: 一种用于转换在两个总线接口之间传输的数据分组的端序域转换电路。 该新颖系统有利地消除了对电路的写入数据路径内的大位开关的任何要求。 相反，endian转换智能被放置在读取数据路径中。 从输入数据分组单独接收双字（双字），字节并行存储到几个不同的先进先出（FIFO）存储器的相同字节位置。 在一个示例中，双字为32位，使用的FIFO存储器数为4。 以这种方式接收整个输入数据分组，增加每个双字的FIFO存储器的写入地址。 根据所需的字节序转换类型，如果根本不存在本发明的字节序转换控制电路，则控制四个典型的FIFO存储器（经由读指针）读取的方式以及它们的数据在 输出总线产生输出数据。 在一个实施例中，在输出总线上产生字节流。 或者，双字通过输出总线以适当的字符串格式发送。 位于数据包头部中的数据描述符定义输入数据包的系统存储器中的端序输入域格式，预期端输出域格式，数据包大小和起始地址。 该新颖的系统非常适合于处理任意大小的数据分组以及从任意字节边界开始的数据分组。

公开(公告)号：US5960007A

公开(公告)日：1999-09-28

申请号：US975644

申请日：1997-11-21

Applicant: Edward L. Grivna

Inventor： Edward L. Grivna

IPC: G06F7/76 ,  H04L7/04 ,  H04N7/56 ,  H04N21/236 ,  H04N21/434 ,  H04J3/06

CPC classification number: G06F7/764 ,  H04L7/042 ,  H04N21/23602 ,  H04N21/4342 ,  H04N7/56

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

公开(公告)号：US5941941A

公开(公告)日：1999-08-24

申请号：US943141

申请日：1997-10-03

Applicant: Satoshi Hasegawa

Inventor： Satoshi Hasegawa

IPC: G06F7/00 ,  G06F7/48 ,  G06F7/76 ,  H03M1/18 ,  G06F7/38

CPC classification number: G06F7/48 ,  G06F7/49942

Abstract: In the case that the bit width of a high-speed internal calculation of CPU or DSP is restricted and the high-speed internal calculation is performed as a fixed-point calculation, and the bit width of the input data of CPU or DSP is different from the bit width of the high-speed internal calculation, the input digital signal is truncated prior to the internal calculation. After the high-speed internal calculation has completed (at step S2-3), the result of the high-speed internal calculation is shifted in the direction reverse to that of the truncation by a predetermined bit width (at step S2-4). Thus, the gain of the output signal of the CPU or DSP is prevented from decreasing while performing the high-speed internal calculation.

Abstract translation: 在CPU或DSP的高速内部计算的位宽被限制并且作为定点计算执行高速内部计算的情况下，CPU或DSP的输入数据的位宽不同 从高速内部计算的位宽度开始，输入数字信号在内部计算之前被截断。 在高速内部计算完成之后（步骤S2-3），高速内部计算的结果沿与截断相反的方向移动预定的位宽（步骤S2-4）。 因此，在执行高速内部计算时，防止CPU或DSP的输出信号的增益减小。

公开(公告)号：US5931895A

公开(公告)日：1999-08-03

申请号：US789430

申请日：1997-01-29

Applicant: Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

Inventor： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

IPC: G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/483 ,  G06F7/74 ,  G06F7/76 ,  G06F7/52

CPC classification number: G06F5/012 ,  G06F7/483

Abstract: A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

Abstract translation: 一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路 移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。 浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在 在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。 在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

公开(公告)号：US5909385A

公开(公告)日：1999-06-01

申请号：US831297

申请日：1997-04-01

Applicant: Takahiro Nishiyama ,  Hiromichi Yamada

Inventor： Takahiro Nishiyama ,  Hiromichi Yamada

IPC: G06F7/38 ,  G06F7/00 ,  G06F7/487 ,  G06F7/506 ,  G06F7/52 ,  G06F7/76 ,  G06F7/50

CPC classification number: G06F7/5338

Abstract: A multiplying apparatus includes a Booth decoder for performing a second-order Booth decode on a multiplier, a Booth selector for generating a partial product except the two high-order digits from the output of the decoder and a multiplicand, a partial product corrector for correcting the two high-order digits of the partial product based on the multiplier and the multiplicand and outputting the corrected result, for cancelling a sign corrected portion of the negative partial product, and a carry save adder for being inputted with the outputs of the Booth selector and the outputs of the corrector and adding them.

Abstract translation: 一种乘法装置，包括：用于在乘法器上执行二阶布斯解码的布斯解码器，用于从解码器的输出和被乘数产生除了两个高位数字之外的部分乘积的布斯选择器，用于校正的部分乘积校正器 基于乘法器和被乘数的部分乘积的两个高阶数字，并输出校正结果，用于取消负部分乘积的符号校正部分，以及进位保存加法器，用于输入布尔选择器的输出 和校正器的输出并添加它们。