公开(公告)号：US20080036712A1

公开(公告)日：2008-02-14

申请号：US11826315

申请日：2007-07-13

申请人： Bo Yong Chung

发明人： Bo Yong Chung

IPC分类号： G09G3/32 ,  H03K19/084 ,  H03K19/20

CPC分类号： H03K19/09441 ,  G09G3/3266 ,  G09G2300/0417 ,  G11C19/00

摘要： An organic light emitting diode display, including pixel circuits coupled to respective data lines and scan lines, a data driver configured to supply data signals to the data lines, and a scan driver configured to provide scan signals to the scan lines, wherein the scan driver includes at least one decoder including a plurality of NOR gates, the decoder configured to provide a first plurality of signals, and a plurality of NAND gates coupled to respective scan lines, the NAND gates being configured to perform a NAND operation on the first plurality of signals and to provide scan signals to the scan lines, wherein all transistors in each of the NOR gates and each of the NAND gates are a same type of MOS transistor.

摘要翻译： 一种有机发光二极管显示器，包括耦合到相应数据线和扫描线的像素电路，配置成向数据线提供数据信号的数据驱动器，以及配置成向扫描线提供扫描信号的扫描驱动器，其中扫描驱动器 包括至少一个包括多个NOR门的解码器，所述解码器被配置为提供第一多个信号，以及耦合到相应扫描线的多个NAND门，所述NAND门被配置为对所述第一多个信号执行NAND运算 信号并向扫描线提供扫描信号，其中每个NOR门和每个NAND门中的所有晶体管都是相同类型的MOS晶体管。

公开(公告)号：US07279936B2

公开(公告)日：2007-10-09

申请号：US11007650

申请日：2004-12-07

申请人： Jörg Gliese ,  Tim Schönauer

发明人： Jörg Gliese ,  Tim Schönauer

IPC分类号： H03K19/20 ,  H03K19/084 ,  H03K19/21 ,  G11C8/00 ,  G06F7/50

CPC分类号： H03K19/17796 ,  H03K19/1736 ,  H03K19/17728

摘要： A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, having four data signal inputs, to which two data signals and the logically complementary data signals thereof can be applied, and having six logic selection elements between the data signal inputs. At a data signal output, the logic combination of the two data signals in accordance with the logic function selected by means of the logic selection elements can be provided as output signal.

摘要翻译： 逻辑基本单元，逻辑基本单元布置和逻辑器件。 逻辑基本单元被提供用于根据可以通过具有四个数据信号输入的多个逻辑选择元件选择的逻辑功能形成两个数据信号的逻辑组合，两个数据信号和逻辑互补 可以应用其数据信号，并且在数据信号输入之间具有六个逻辑选择元件。 在数据信号输出端，可以提供根据逻辑选择元件选择的逻辑功能的两个数据信号的逻辑组合作为输出信号。

公开(公告)号：US20060192591A1

公开(公告)日：2006-08-31

申请号：US11067825

申请日：2005-02-28

申请人： Wing Luk

发明人： Wing Luk

IPC分类号： H03K19/084

CPC分类号： H03K19/09421 ,  H03K19/0963

摘要： A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode and changing a voltage of a source of the gated diode in an evaluation mode. One or more isolation devices may be connected between each small amplitude signal and a gate of the gated diode, wherein the isolation device passes the small amplitude signal to the gate of the gated diode in the sampling mode, and isolates the small amplitude signal from the gate in the evaluation mode for amplification and performing fast logic operations (logic functions). The disclosed gated diode logic circuits overcome the Vt variation problem in FETs by detecting and amplifying the small logic signals utilizing gated diodes that have relatively low Vt variation. The amplified signals may then be processed by conventional logic circuits to perform certain logic functions in a gated diode logic circuit. The Vt variation of the gated diode is relatively small compared to the small logic signal amplitude and can be controlled relatively precisely. Typically, Vt of the gated diode can be set to a fraction of the small logic signal amplitude. Thus, in a gated diode logic circuit, the gated diode circuit can sense and amplify the small logic signals sufficiently to perform the various logic operations in conjunction with conventional logic circuits. The output(s) of the gated diode logic circuit can be of a standard full CMOS voltage swing, or can be scaled down in amplitude and further processed by other gated diode logic circuits.

摘要翻译： 公开了一种称为门控二极管逻辑电路的逻辑电路，其中通过以采样模式将小振幅信号施加到门控二极管的栅极，可以感测和放大小振幅信号，通常为电源电压的一小部分， 在评估模式下改变门控二极管的源极的电压。 每个小振幅信号和门控二极管的栅极之间可以连接一个或多个隔离器件，其中隔离器件以采样模式将小振幅信号传递到门控二极管的栅极，并将小振幅信号与 门在评估模式下进行放大并执行快速逻辑运算（逻辑功能）。 公开的门控二极管逻辑电路通过利用具有相对较低V 0变化的门控二极管检测和放大小逻辑信号来克服FET中的V 0变化问题。 然后，放大的信号可以由常规逻辑电路来处理，以在门控二极管逻辑电路中执行某些逻辑功能。 门控二极管的V OUT变化与小逻辑信号幅度相比相对较小，并且可以被相对精确地控制。 通常，门控二极管的V OUT可以被设置为小逻辑信号幅度的一部分。 因此，在门控二极管逻辑电路中，门控二极管电路可以充分感测和放大小逻辑信号，以结合常规逻辑电路执行各种逻辑运算。 门控二极管逻辑电路的输出可以是标准的全CMOS电压摆幅，或者可以在幅度上缩小，并由其他门控二极管逻辑电路进一步处理。

公开(公告)号：US6020763A

公开(公告)日：2000-02-01

申请号：US771124

申请日：1996-12-20

申请人： Betrand Gabillard

发明人： Betrand Gabillard

IPC分类号： G11C8/10 ,  G11C11/418 ,  H03K19/084

CPC分类号： G11C8/10 ,  G11C11/418

摘要： A self-clocked apparatus for eliminating race condition in high speed decoders is provided. In multi-stage decoders, a first stage is generally composed of predecoder blocks while a second stage is generally composed of decoder/driver blocks. Each predecoder block receives several address bits and outputs a high or low level signal depending on the address bit's state. Each decoder/driver block receives the output signal of the corresponding predecoder block, and outputs a signal selecting or not selecting a connected line. The self-clocked apparatus of the invention is cross-connected between adjacent predecoder blocks such that the ith decoder/driver block is controlled by the i+1th predecoder block, and conversely. No external clock signal is used, and no time margins are required. Furthermore, the invention provides a robust electrical design.

摘要翻译： 提供了一种用于消除高速解码器中的竞争条件的自定时装置。 在多级解码器中，第一级通常由预解码器块组成，而第二级通常由解码器/驱动器块组成。 每个预解码器块接收多个地址位，并根据地址位的状态输出高电平或低电平信号。 每个解码器/驱动器块接收相应的预解码器块的输出信号，并输出选择或不选择连接的线路的信号。 本发明的自定时装置在相邻的预解码器块之间交叉连接，使得第i个解码器/驱动器块由第i + 1个预解码器块控制，反之亦然。 不使用外部时钟信号，不需要时间间隔。 此外，本发明提供了一种坚固的电气设计。

公开(公告)号：US5682110A

公开(公告)日：1997-10-28

申请号：US855958

申请日：1992-03-23

申请人： Robert N. Rountree

发明人： Robert N. Rountree

IPC分类号： H03K19/094 ,  H03K19/084

CPC分类号： H03K19/09429

摘要： A low capacitance bus driver circuit includes, in this example, P-channel and N-channel output transistors with input gates connected by means of CMOS pass gates to a common input terminal and having respective P-channel and N-channel transistors connected to the input gates of the output transistors so as to place them in a high impedance state when the CMOS pass gates are disabled. Input capacitance of the bus driver circuit is greatly reduced by elimination of CMOS gate capacitance when the bus driver is enabled. When the bus driver is not enabled, it provides optimal performance of a single gate delay from input to output without the need for series connected output devices or correspondingly higher input capacitance.

摘要翻译： 低电容总线驱动器电路在本例中包括P沟道和N沟道输出晶体管，其输入栅极通过CMOS栅极连接到公共输入端并且具有连接到第二栅极的相应P沟道和N沟道晶体管 输入晶体管的输入栅极，以便当CMOS通道禁止时将它们置于高阻抗状态。 当总线驱动器使能时，通过消除CMOS栅极电容，可大大减少总线驱动电路的输入电容。 当总线驱动器未使能时，它提供从输入到输出的单个门延迟的最佳性能，而不需要串联连接的输出设备或相应较高的输入电容。

公开(公告)号：US5668488A

公开(公告)日：1997-09-16

申请号：US341636

申请日：1994-11-17

申请人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

发明人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/084

CPC分类号： H03K19/00323 ,  H03K19/0027

摘要： An input buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The input buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix to produce an output which transitions when a signal input to the switch matrix transitions through a predetermined value.

摘要翻译： 输入缓冲器，用于对由高密度可编程逻辑器件（PLD）的开关矩阵引入的RC时间延迟进行补偿。 输入缓冲器包括提供输入阈值的电路，其变化以补偿开关矩阵的RC延迟，以产生当输入到开关矩阵的信号转变为预定值时转变的输出。

公开(公告)号：US5473271A

公开(公告)日：1995-12-05

申请号：US15691

申请日：1993-02-09

申请人： Wendell L. Little ,  Stephen N. Grider ,  Joseph W. Triece

发明人： Wendell L. Little ,  Stephen N. Grider ,  Joseph W. Triece

IPC分类号： G06F1/08 ,  H03K19/003 ,  H03K19/084

CPC分类号： G06F1/08 ,  H03K19/00361

摘要： A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.

摘要翻译： 微处理器板载RAM通过寻址和一个存储器单元的子集提供通常的随机存取，其内容在与数据总线并行的辅助总线上连续可用。 当RAM子集包含用于寄存器间接寻址的寄存器时，该辅助总线可用于寄存器间接寻址，而不需要单独的寄存器读取。 处理器还具有两级输出驱动器，用于限制最大输出电流和反馈控制的时钟周期分区。

公开(公告)号：US5378941A

公开(公告)日：1995-01-03

申请号：US983467

申请日：1992-11-30

申请人： Yoji Nishio ,  Ikuro Masuda ,  Kazuo Kato ,  Shigeo Kuboki ,  Masahiro Iwamura

发明人： Yoji Nishio ,  Ikuro Masuda ,  Kazuo Kato ,  Shigeo Kuboki ,  Masahiro Iwamura

IPC分类号： H03K19/08 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/73 ,  H03K19/173 ,  H03K19/02 ,  H03K19/084

CPC分类号： H01L27/11896

摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.

摘要翻译： 高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个 输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。 每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

公开(公告)号：US4745308A

公开(公告)日：1988-05-17

申请号：US467681

申请日：1983-02-18

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K19/003 ,  H03K19/082 ,  H03K17/16 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/00353 ,  H03K19/0823

摘要： A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

摘要翻译： 公开了具有能够呈现有效高电平，有效低电平或高阻抗状态的输出的三态门，其消除了在从高阻抗状态向高电平跃迁期间的输出中的毛刺。 输出装置包括用于向输出端提供电流的第一晶体管和用于从输出引出电流的第二晶体管。 相位分离装置确定第一和第二晶体管的电导率。 逻辑装置响应输入信号和输出使能信号两者并耦合到相位分离装置。 逻辑装置包括电平设置装置，其确保在输出从有效高电平转换到高阻抗状态期间第二晶体管不导通。

公开(公告)号：US4713561A

公开(公告)日：1987-12-15

申请号：US15512

申请日：1987-02-10

申请人： Kazuyoshi Yamada

发明人： Kazuyoshi Yamada

IPC分类号： H03K17/04 ,  H03K19/013 ,  H03K19/0944 ,  H03K19/003 ,  H03K17/30 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/09448 ,  H03K19/013

摘要： A transistor circuit includes an input terminal, an output terminal, a first transistor having a collector connected to the output terminal, a second transistor having a collector-emitter passage connected between the collector of the first transistor and the input terminal, a PN junction element such as a diode or a base-emitter junction of another transistor, which is connected between the input terminal and the base of the first transistor, a first resistor connected between the emitter and base of the second transistor, and a second resistor connected between the base and collector of the second transistor.

摘要翻译： 晶体管电路包括输入端子，输出端子，具有连接到输出端子的集电极的第一晶体管，具有连接在第一晶体管的集电极和输入端子之间的集电极 - 发射极通道的第二晶体管，PN结元件 例如连接在第一晶体管的输入端子和基极之间的另一个晶体管的二极管或基极 - 发射极结，连接在第二晶体管的发射极和基极之间的第一电阻器，以及连接在第二晶体管的发射极和基极之间的第二电阻器 第二晶体管的基极和集电极。