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1.发明授权公开(公告)号：US09583587B2
公开(公告)日：2017-02-28
申请号：US14902220
申请日：2014-07-23
发明人： Wanli Wang , Xiaoshe Deng , Genyi Wang , Xuan Huang
IPC分类号： H01L21/33 , H01L21/22 , H01L21/38 , H01L29/66 , H01L29/739 , H01L29/10 , H01L29/06 , H01L21/265 , H01L21/266 , H01L21/225 , H01L21/324
CPC分类号： H01L29/66348 , H01L21/2253 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/063 , H01L29/1095 , H01L29/7397
摘要： A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.
摘要翻译： 一种用于制造注射增强绝缘栅双极晶体管的方法，包括以下步骤：提供n型衬底（12）; 在n型衬底（12）上形成p型掺杂层（14）。 在p型掺杂层（14）上形成硬质层（20）。 通过蚀刻在p型掺杂层（14）上形成延伸到n型衬底（12）的沟槽（40）。 在凹槽（40）的侧壁和底部上形成n型掺杂层（50）; 去除硬层（20）; p型掺杂层（14）的p型杂质和n型掺杂层（50）的n型杂质一起被驱动，其中p型杂质被扩散以形成p型基极区域 （60），并且n型杂质扩散以形成n型缓冲层（70）; 在凹槽（40）的表面上形成栅极氧化物介电层（80）; 并且在其中形成有栅极氧化物介电层（80）的沟槽中沉积多晶硅层（90）。 在注入增强型绝缘栅双极晶体管的制造方法中，p型掺杂层（14）和n型掺杂层（50）一起被驱动以形成p型基极区（60）和 n型缓冲层（70）仅需要一个驱动工艺，与用于制造注射增强型绝缘栅双极晶体管的传统方法相比，生产周期缩短。
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2.发明授权Trench DMOS device with reduced gate resistance and manufacturing method thereof 有权具有降低的栅极电阻的沟槽DMOS器件及其制造方法公开(公告)号：US09401422B2
公开(公告)日：2016-07-26
申请号：US14651706
申请日：2013-12-31
发明人： Zheng Bian
IPC分类号： H01L29/78 , H01L21/265 , H01L29/40 , H01L29/49 , H01L29/66 , H01L29/417 , H01L29/423 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7813 , H01L21/265 , H01L29/0619 , H01L29/1095 , H01L29/401 , H01L29/41766 , H01L29/42372 , H01L29/4916 , H01L29/66681 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.
摘要翻译： 沟槽型DMOS器件包括作为公共漏极区域的衬底，形成在衬底上的有源区和分压环，以及形成在衬底上的第一电介质层。 多个沟槽位于第一电介质层上，并且沟槽从第一电介质层的表面延伸到衬底的内部。 沟槽包括分布在有源区中的至少一个第一沟槽和在有源区之外的第二沟槽。 在沟槽中形成栅极氧化层，填充多晶硅以形成栅极。 有源区还包括在源电极区下面的源电极区和P型重掺杂区。 第二电介质层覆盖第一电介质层和多个沟槽。 金属层覆盖第二电介质层以形成第一电极区域和第二电极区域。
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公开(公告)号：US09236306B2
公开(公告)日：2016-01-12
申请号：US14130476
申请日：2012-11-28
发明人： Hsiaochia Wu , Shilin Fang , Tsehuang Lo , Zhengpei Chen , Shu Zhang , Yanqiang He
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823412 , H01L21/823456 , H01L21/8238 , H01L21/823807 , H01L21/82385 , H01L27/0922
摘要： A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.
摘要翻译： 根据本说明书的制造半导体器件的方法解决了现有技术中的问题，即LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件的击穿。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 该方法适用于BCD处理等。
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公开(公告)号：US09952609B2
公开(公告)日：2018-04-24
申请号：US15327916
申请日：2015-08-18
摘要： A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the reference voltage determining module (300) controls an enablement of the error amplifier (200) according to whether the voltage reference source module (100) is completely started, the error amplifier (200) controls ON/OFF of the power transmission device (400) according to the reference voltage provided by the voltage reference source module (100) and a feedback voltage provided by the feedback module (500). A chip having the above low dropout linear regulator circuit and a electronic device having the above chip are provided.
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公开(公告)号：US09520400B2
公开(公告)日：2016-12-13
申请号：US14398849
申请日：2013-05-19
发明人： Shizhen Sun , Hao Fang , Yong Gu
IPC分类号： H01L27/105 , H01L21/28 , H01L29/66 , H01L29/788 , H01L27/115 , H01L21/283 , H01L29/423
CPC分类号： H01L27/1052 , H01L21/28273 , H01L21/283 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.
摘要翻译： 在本公开中提供了NOR闪存及其制造方法，它们在闪存的领域中。 在制造方法中，在栅极堆叠结构的第二多晶硅层上形成掩模电介质层。 此外，掩模介电层的一部分被图案化地蚀刻以暴露靠近源极的第二多晶硅层的部分。 此外，暴露的第二多晶硅层自对准以形成金属硅化物层。 因此，在NOR闪速存储器中，未蚀刻的掩模介电层基本上位于NOR闪存的金属硅化物层和漏极接触孔之间。 栅电极和漏电极之间的漏极电流小，上述制造方法不复杂，工艺窗口大，副作用小，有利于大规模生产。
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公开(公告)号：US09136229B2
公开(公告)日：2015-09-15
申请号：US14130427
申请日：2012-08-09
申请人： Meng Dai
发明人： Meng Dai
CPC分类号： H01L23/60 , H01L27/0262 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device is provided. A proper trigger voltage is determined by providing an ESD doped injection layer into a PNPN structure and adjusting the injection energy and dosage of the ESD doped injection layer; a proper holding voltage is obtained by adjusting the size of the ESD doped injection layer, thus preventing the latch-up. The self-isolation effect of the electrostatic discharge protection device is formed on the basis of an epitaxial wafer high voltage process or a silicon-on-insulator (SOI) wafer high voltage process, the ESD protective device of the present invention can prevent the device from being falsely triggered due to noise interference. Compared with other known ESD protection devices, the device has the same electrostatic protection ability, much smaller area, and much lower cost.
摘要翻译： 提供一种静电放电（ESD）保护装置。 通过将ESD掺杂注入层提供到PNPN结构中并调整ESD掺杂注入层的注入能量和剂量来确定适当的触发电压; 通过调整ESD掺杂注入层的尺寸来获得适当的保持电压，从而防止闩锁。 基于外延晶片高压工艺或绝缘体上硅（SOI）晶片高压工艺，形成静电放电保护器件的自隔离效果，本发明的ESD保护器件可以防止器件 由于噪音干扰而被误导。 与其他已知的ESD保护器件相比，该器件具有相同的静电保护能力，面积小得多，成本低得多。
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公开(公告)号：US10254353B2
公开(公告)日：2019-04-09
申请号：US15327956
申请日：2015-06-30
IPC分类号： G01R31/40 , G01R19/165 , G01R15/04 , G06F1/28
摘要： A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the voltage divider (110) is connected to a positive input of the comparator (130), the reference voltage source (120) is connected to an inverted input of the comparator (130), the time sequence control module (140) is connected to an output of the comparator (130), an output of the time sequence control module (140) serves as an output of the brown-out detection circuit; when a duration of a power supply voltage lower than a reference voltage is not shorter than a preset time, the time sequence control module (140) controls the output of the brown-out detection circuit to be inverted from a high level to a low level.
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公开(公告)号：US09834437B2
公开(公告)日：2017-12-05
申请号：US15327230
申请日：2015-07-31
发明人： Errong Jing
CPC分类号： B81C1/00182 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2203/058 , B81C1/00603 , B81C2201/0109 , B81C2201/0111
摘要： A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate separated from a peripheral region, wherein the upper electrode plate and the peripheral region are connected by only using a cantilever beam, and forming, on the peripheral region, a recessed portion exposing the buried oxide layer; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and is close to one end of the cantilever beam; exposing the second silicon layer, and suspending the upper electrode plate and the cantilever beam; and respectively forming an upper contact electrode and a lower contact electrode on the second silicon layer.
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公开(公告)号：US09006867B2
公开(公告)日：2015-04-14
申请号：US14364933
申请日：2012-11-20
发明人： Xinwei Zhang , Changfeng Xia , Chengjian Fan , Wei Su
IPC分类号： H01L21/66 , H01L21/306 , H01L21/308
CPC分类号： H01L22/30 , H01L21/30608 , H01L21/3083 , H01L22/12
摘要： A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
摘要翻译： 提供了硅湿蚀刻深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽，其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和W1，Wu = du / 0.71，W1 = du / 0.71，其中du是要监测的最大湿蚀刻深度，d1是湿蚀刻深度的最小值 被监视。 该方法包括：根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻，形成待监测的蚀刻凹槽和用于监测凹槽深度的结构，然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度，并且获得更高的监视精度。
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公开(公告)号：US09975766B2
公开(公告)日：2018-05-22
申请号：US15312146
申请日：2015-05-05
发明人： Yonggang Hu , Guoping Zhou
IPC分类号： B81C1/00
CPC分类号： B81C1/00619 , B81C1/00 , B81C2201/0133 , B81C2201/0142
摘要： An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is more precise, and the uniformity and the homogeneity of the formed support beam are better.
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