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    HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL
    3.
    发明申请
    HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL 有权

    公开(公告)号：US20250149499A1

    公开(公告)日：2025-05-08

    申请号：US18504526

    申请日：2023-11-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ravi Prakash SRIVASTAVA ,  Matthew Charles GORFIEN

    IPC: H01L23/00

    Abstract: A method for hybrid bonding a first semiconductor substrate to a second semiconductor substrate includes forming a first plurality of metal pads on a face of the first substrate, forming a second plurality of metal pads on a face of the second substrate, selectively forming a first dielectric layer over a first insulating material of the first substrate, selectively forming a second dielectric layer over a second insulating material of the second substrate, placing the face of the first substrate against the face of the second substrate so that the first dielectric layer contacts the second dielectric layer, and heating the first substrate and the second substrate to bond the first plurality of metal pads to the second plurality of metal pads. The first and second dielectric layers may be formed by an area selective deposition process.

    SIGNAL PROPAGATION SIMULATION INCLUDING PHOTONIC DEVICE-TO-PHOTONIC DEVICE CONNECTIVITY AWARENESS
    4.
    发明申请
    SIGNAL PROPAGATION SIMULATION INCLUDING PHOTONIC DEVICE-TO-PHOTONIC DEVICE CONNECTIVITY AWARENESS 有权

    公开(公告)号：US20250148181A1

    公开(公告)日：2025-05-08

    申请号：US18503212

    申请日：2023-11-07

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Bradley A. Orner ,  Romain H.A. Feuillette ,  Vivienne A.B. Miller ,  Petar Ivanov Todorov ,  Stephen T. Burgess

    IPC: G06F30/3308 ,  G02B27/00

    Abstract: Disclosed are a photonic integrated circuit (PIC) design system and method including optical signal propagation simulation with coupling awareness to account for transition loss due to a difference between at least one specific physical parameter (e.g., curvature radius, material composition, etc.) in optically coupled photonic devices. Coupling awareness can be achieved by including, within a bus of a netlist between the photonic devices, at least one pair of physical data pins: one associated with a specific physical parameter in the light emitting photonic device and the other associated with the specific physical parameter in the light receiving photonic device. Alternatively, coupling awareness can be achieved by running a utility to identify a parameter mismatch between the light emitting and receiving photonic devices, developing a custom coupling cell to account for the mismatch, and inserting the custom coupling cell into a design layout for the PIC.

    Defect detection system for cavity in integrated circuit
    6.
    发明授权
    Defect detection system for cavity in integrated circuit 有权

    公开(公告)号：US12292470B2

    公开(公告)日：2025-05-06

    申请号：US18172488

    申请日：2023-02-22

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Zhuojie Wu ,  Yunyao Jiang

    IPC: G01R31/28 ,  G02B6/12

    Abstract: A structure provides a defect sensor for a cavity in an integrated circuit (IC). The structure includes a cavity defined in a substrate. A boundary is located where the cavity meets with a cavity-free area of the substrate. A metal line is arranged in a serpentine path in both a vertical and a horizontal direction and crosses the boundary. A controller may be provided that is configured to, in response to a change in an electrical characteristic of a signal through the metal line, generate an indication of the presence of a defect and/or change operation of at least one component of the IC. The structure may find application relative to a photonics integrated circuit (PIC) structure including an optical waveguide with a cavity under the optical waveguide.

    Cell layouts
    8.
    发明授权
    Cell layouts 有权

    公开(公告)号：US12288782B2

    公开(公告)日：2025-04-29

    申请号：US17679655

    申请日：2022-02-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Juhan Kim ,  Sangmoon J. Kim ,  Mahbub Rashed ,  Navneet K. Jain

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/417

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

    Photonic structure with waveguide-to-photodetector coupler oriented along sidewall of a photodetector
    9.
    发明授权
    Photonic structure with waveguide-to-photodetector coupler oriented along sidewall of a photodetector 有权

    公开(公告)号：US12278297B2

    公开(公告)日：2025-04-15

    申请号：US18050147

    申请日：2022-10-27

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yusheng Bian

    IPC: H01L31/0232 ,  G02B6/12 ,  H01L31/105 ,  G02B6/42

    Abstract: Disclosed are embodiments of a photonic structure with at least one tapered coupler positioned laterally adjacent and along the length of a sidewall of a layer, such as a light absorption layer (LAL), of a photodetector to facilitate mode matching. Some embodiments include a vertically oriented photodetector, which is on an insulator layer and has an LAL stacked between bottom and top semiconductor layers, and a coupler, which is on the insulator layer positioned laterally adjacent to the photodetector and has stacked cores with one of the cores being at the same level as the LAL. Other embodiments include a horizontally oriented photodetector, which is on an insulator layer and has an LAL on a recessed section of a bottom semiconductor layer between side sections, and coupler(s), which is/are above side section(s) of the bottom semiconductor layer and, thus, positioned laterally adjacent to one or both sides of the LAL.

    COMPACT MEMORY-IN-PIXEL DISPLAY STRUCTURE
    10.
    发明申请
    COMPACT MEMORY-IN-PIXEL DISPLAY STRUCTURE 有权

    公开(公告)号：US20250118245A1

    公开(公告)日：2025-04-10

    申请号：US18482114

    申请日：2023-10-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

    IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

    Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

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