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公开(公告)号：US12111407B2
公开(公告)日：2024-10-08
申请号：US17024874
申请日：2020-09-18
CPC分类号： G01S5/0215 , G01S5/0018 , G01S5/021 , G01S5/08 , H04L1/08 , H04W56/001 , H04W72/0446 , H04W4/80
摘要： A system having a locator device and a plurality of tag devices is disclosed. The locator device comprises an antenna array allowing it to determine an angle of arrival for incoming signals from each of the plurality of tag devices. The system also defines a sequence of time slots, where each time slot has a specific function. The sequence may start with a locator time slot, where the locator device transmits a packet that informs all of the tag devices that this is the start of the sequence. A sync slot follows the locator time slot, where new tag devices may transmit a sync request to the locator device. Upon receipt of a sync request, the locator device assigns the new tag device a tag slot. Following the sync slot are a plurality of tag slots, where each tag device transmits an AoA packet during its assigned tag slot.
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2.发明公开公开(公告)号：US20240334400A1
公开(公告)日：2024-10-03
申请号：US18127189
申请日：2023-03-28
发明人： Karthik Gunturi , Sunit Pujari , Ravikiran Nemali
IPC分类号： H04W72/0446 , H04L69/166 , H04W4/80
CPC分类号： H04W72/0446 , H04L69/166 , H04W4/80
摘要： A system and method for reducing packet error rates for L2CAP PDUs with large payloads is disclosed. The Bluetooth device fragments the large payload in several packets in accordance with well known algorithms. However, prior to transmission, the Bluetooth device redistributes the payload among these packets to reduce the maximum payload that is transmitted in one packet. In one embodiment, the Optimum Slot Utilization algorithm is used to determine the number and types of packets to be used, as well as the payloads in each packet. Once this is determined, the Bluetooth device then redistributes the payload across these packets to reduce the size of the largest payload that is transmitted in any packet, while still maintaining the same number of packets.
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公开(公告)号：US20240333569A1
公开(公告)日：2024-10-03
申请号：US18193668
申请日：2023-03-31
IPC分类号： H04L27/26
CPC分类号： H04L27/26025 , H04L27/2614
摘要： In one aspect, an apparatus comprises: a radio frequency (RF) front end circuit to receive and process an RF signal comprising a packet, the RF front end circuit to output a digital signal comprising the packet; and a baseband circuit coupled to the RF front end circuit. The baseband circuit may comprise: a demodulator to receive the digital signal comprising a plurality of extended and modulated symbols and to: perform a plurality of operations on at least some of a first block of the plurality of extended and modulated symbols according to a reverse recipe of operations to obtain a processed first block of the plurality of extended and modulated symbols; aggregate the processed first block of the plurality of extended and modulated symbols into an aggregated symbol; and demodulate the aggregated symbol to obtain at least one soft value.
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公开(公告)号：US20240333316A1
公开(公告)日：2024-10-03
申请号：US18322639
申请日：2023-05-24
CPC分类号： H04B1/0028 , H04B1/12
摘要： A receiver includes: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) signal comprising a packet; an analog-to-digital converter (ADC) to receive and digitize the processed incoming RF signal into a digital signal; a packet detector to detect the packet; an estimation circuit to determine a carrier frequency offset (CFO) estimate based at least in part on a preamble of the packet; an averager to determine a CFO average value for a plurality of packets communicated between a device pair combination of the receiver and a transmitter; and a compensation circuit to compensate for CFO between the device pair combination based at least in part on the CFO average value.
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公开(公告)号：US12107588B2
公开(公告)日：2024-10-01
申请号：US18076058
申请日：2022-12-06
发明人： John M. Khoury , Michael Wu
CPC分类号： H03L7/0991 , H03B5/32
摘要： A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.
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公开(公告)号：US12106973B2
公开(公告)日：2024-10-01
申请号：US17513037
申请日：2021-10-28
发明人： Erwin Hendarto
IPC分类号： H01L21/56 , B23K26/362 , B23K101/40 , H01L21/67 , H01L23/00 , H01L23/31 , H01L23/552
CPC分类号： H01L21/565 , B23K26/362 , H01L21/67075 , H01L23/3157 , H01L23/552 , H01L24/49 , B23K2101/40 , H01L2924/01047 , H01L2924/18165
摘要： In one embodiment, a method includes: laser ablating an encapsulant of a semiconductor package, until a threshold amount of the encapsulant remains above one or more die of the semiconductor package; and providing at least one drop of acid onto a surface of the ablated semiconductor package to acid etch for a first time duration, to remove a remaining portion of the encapsulant above the one or more die, where after the acid etch, a die of interest is exposed and the silver bond wires of the semiconductor package are preserved.
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公开(公告)号：US12086597B2
公开(公告)日：2024-09-10
申请号：US17361250
申请日：2021-06-28
CPC分类号： G06F9/325 , G06F9/3455
摘要： An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.
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公开(公告)号：US20240295891A1
公开(公告)日：2024-09-05
申请号：US18177842
申请日：2023-03-03
发明人： Sagar Kumar
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A voltage regulator includes a first circuit to generate a difference signal based on an input reference voltage, a regulated output voltage, and a signal on a feedback node. The voltage regulator includes a second circuit to provide the regulated output voltage on the output node based on the difference signal. The second circuit includes a first transistor coupled to receive the difference signal, a first feedback circuit to provide a first feedback signal to the feedback node, and a second feedback circuit to provide a second feedback signal to the feedback node. An open loop frequency response of the voltage regulator has a first pole and a second pole and the first feedback signal may adjust the frequency of the second pole based on a load current. The second feedback signal may adjust loop gain based on the load current.
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公开(公告)号：US20240292331A1
公开(公告)日：2024-08-29
申请号：US18175623
申请日：2023-02-28
发明人： Yi Shen Yeh , Yan Zhou , Marc Leroux
CPC分类号： H04W52/0229 , H04L27/02
摘要： In an embodiment, an apparatus includes a baseband processor comprising: a packet generation circuit to generate a wake-up packet comprising information to cause a first receiver to trigger a wake-up of a second receiver; an encoder to encode the wake-up packet with Manchester encoding to output Manchester encoded on-off keying (MOOK) data; and a modulator coupled to the encoder to receive random data and modulate the random data. This modulated random data may be amplitude modulated with the MOOK data to realize a radio frequency (RF) signal comprising the MOOK data that is to be transmitted to one or more receivers.
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公开(公告)号：US20240276537A1
公开(公告)日：2024-08-15
申请号：US18169572
申请日：2023-02-15
IPC分类号： H04W72/566
CPC分类号： H04W72/569 , H04W80/02
摘要： A technique for reducing latency of high priority asynchronous traffic in the presence of isochronous traffic of a Bluetooth™ Low Energy communications system includes communicating an Asynchronous Connection Link (ACL) payload using a Connected Isochronous Stream (CIS) event. A bit in a header of a host-controller interface packet indicates to the controller that an ACL packet is a high priority ACL packet. The controller replaces the payload of a CIS event with the payload of the high priority ACL packet and the controller encodes a bit in a header of the CIS packet to signal to the receiving device that a corresponding CIS event contains an ACL payload. The controller transmits the CIS packet in the corresponding CIS event and the receiving device applies ACL handling of the CIS event in response to decoding the bit in the header of the CIS packet.
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