公开(公告)号：US20240071470A1

公开(公告)日：2024-02-29

申请号：US18499449

申请日：2023-11-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

发明人： He-Zhou WAN ,  Xiu-Li YANG ,  Mu-Yang YE ,  Yan-Bo SONG

IPC分类号： G11C11/408 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094

CPC分类号： G11C11/4085 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4094

摘要： A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

公开(公告)号：US11876088B2

公开(公告)日：2024-01-16

申请号：US17527883

申请日：2021-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： Yang Zhou ,  Liu Han ,  Qingchao Meng ,  XinYong Wang ,  ZeJian Cai

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L25/065 ,  H01L23/48 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/00 ,  G06F30/392 ,  H01L21/74

CPC分类号： H01L27/0207 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76898 ,  H01L21/823892 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0928 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

公开(公告)号：US20230402446A1

公开(公告)日：2023-12-14

申请号：US18447857

申请日：2023-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED ,  TSMC CHINA COMPANY, LIMITED

发明人： Liu HAN ,  Xin Yong WANG ,  Qingchao MENG ,  Huaixin XIAN ,  Jing DING

IPC分类号： H01L27/02 ,  H03K19/00 ,  H01L27/06

CPC分类号： H01L27/0207 ,  H03K19/0016 ,  H01L27/0629

摘要： A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

公开(公告)号：US11705175B2

公开(公告)日：2023-07-18

申请号：US17883364

申请日：2022-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： XiuLi Yang ,  Ching-Wei Wu ,  He-Zhou Wan ,  Kuan Cheng ,  Luping Kong

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C8/18 ,  G11C7/106 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

摘要： A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

公开(公告)号：US20230049698A1

公开(公告)日：2023-02-16

申请号：US17973823

申请日：2022-10-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

发明人： He-Zhou WAN ,  Xiu-Li YANG ,  Mu-Yang YE ,  Yan-Bo SONG

IPC分类号： G11C11/408 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094

摘要： A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

公开(公告)号：US20220375512A1

公开(公告)日：2022-11-24

申请号：US17883364

申请日：2022-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： XiuLi YANG ,  Ching-Wei WU ,  He-Zhou WAN ,  Kuan CHENG ,  Luping KONG

IPC分类号： G11C11/418

摘要： A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

公开(公告)号：US10937477B1

公开(公告)日：2021-03-02

申请号：US16582514

申请日：2019-09-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： XiuLi Yang ,  Ching-Wei Wu ,  He-Zhou Wan ,  Kuan Cheng ,  Luping Kong

IPC分类号： G11C8/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/08 ,  G11C11/419 ,  G11C7/10 ,  G11C11/418

摘要： A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.

公开(公告)号：US20240161798A1

公开(公告)日：2024-05-16

申请号：US18422908

申请日：2024-01-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

发明人： Xiu-Li YANG ,  He-Zhou WAN ,  Mu-Yang YE ,  Lu-Ping KONG ,  Ming-Hung CHANG

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/222 ,  G11C2207/12

摘要： A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

公开(公告)号：US20240021225A1

公开(公告)日：2024-01-18

申请号：US18476030

申请日：2023-09-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

发明人： Xiu-Li YANG ,  He-Zhou WAN ,  Mu-Yang YE ,  Lu-Ping KONG ,  Ming-Hung CHANG

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C7/1069 ,  G11C7/222 ,  G11C7/1096 ,  G11C2207/12

摘要： A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

公开(公告)号：US20230326501A1

公开(公告)日：2023-10-12

申请号：US18336428

申请日：2023-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited ,  TSMC China Company Limited

发明人： He-Zhou WAN ,  Xiu-Li YANG ,  Pei-Le LI ,  Ching-Wei WU

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C5/14 ,  G11C8/10

CPC分类号： G11C7/109 ,  G11C7/1096 ,  G11C7/1069 ,  G11C7/1063 ,  G11C7/12 ,  G11C7/1084 ,  G11C5/148 ,  G11C5/147 ,  G11C8/10 ,  G11C7/1057

摘要： A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.