Abstract:
A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer or a printed circuit board. The core of the bump is made of polymeric material, and coated with a conductive material. In particular, the compliant bump is disposed on the one side of the conductive contact structure that includes both the bump and the testing area, wherein the testing area allows the area to be functionality tested, so as to prevent damage of the coated conductive material over the compliant bump during a probe testing.
Abstract:
A circular polarizer comprising a single linear polarizer producing a linear state of polarization and at least one phase retardation film layered with the single linear polarizer. In a first embodiment, the at least one phase retardation film includes at least one uniaxial A-plate phase retardation film and at least one uniaxial C-plate phase retardation film. In a second embodiment of the invention, the circular polarizer includes a linear polarizer and at least one biaxial phase retardation film layered with the linear polarizer. In another example of the circular polarize of the second embodiment, at least one uniaxial A-plate phase retardation film and/or at least one uniaxial C-plate phase retardation film is also layer with the linear polarize and the biaxial phase retardation film.
Abstract:
A method of fabricating an active layer thin film by a metal-chalcogenide precursor solution is provided, including the steps of: synthesizing a metal-chalcogenide precursor containing benzyl or benzyl derivative; dissolving the precursor in a solvent to produce a precursor solution, wherein a chalcogen element or compound can be added to the precursor solution to adjust the molar ratio of metal ion to chalcogen; and then applying the precursor solution onto a substrate in a specific coating manner, to form a film of the metal-chalcogenide after a curing process. Thereby, the existing method wherein an amorphous silicon active layer film is fabricated by plasma enhanced chemical vapor deposition (PECVD) is replaced.
Abstract:
A transflective liquid crystal display with uniform cell gap configuration throughout the transmissive and the reflective display region is invented. Mutually complementary common electrode pattern and reflector pattern or mutually complementary ITO pixel electrode pattern and reflector pattern produce an electric field in the transmissive display region that has a uniform longitudinal field and an electric field in the reflective display region that is a fringing field. An initially vertically aligned negative dielectric anisotropic nematic liquid crystal material between the electrodes forms a smaller tilt angle with respect to the substrate normal in the reflective display region while a larger tilt angle with respect to the substrate normal in the transmissive display region. Consequently, the ambient incident light experiences smaller phase retardation in the reflective display region while the light from the backlight source experiences larger phase retardation. Since the ambient light passes through the reflective display region twice while the light from the backlight source passes through the transmissive display region only once, by properly designing the electrodes and the reflector width, the light from both ambient light source and backlight source will experience almost the same phase retardation in both reflective and transmissive display regions. As a result, the electro-optical performance curves of both-transmissive display mode and reflective display mode overlap.
Abstract:
Systems for displaying images. A representative system incorporates an electroluminescent diode that includes a composite electrode structure. Particularly, the composite electrode structure comprises a layer containing alkali or alkaline earth compounds, and a metal oxide layer or semiconductor layer. Wherein, the alkali or alkaline earth compound has carbonyl group or fluorine.
Abstract:
Systems for displaying images are provided. A representative system incorporates a digital data sampling circuit with N stage data inputs. The first stage flip-flop outputs a first output signal. The second stage flip-flop outputs a second output signal. The first stage sample latch circuit receives digital data according to a first control signal. The first stage logic circuit comprises a first converter for inverting the second output signal and generating a first inverse logic signal, and generates the first control signal according to the first output signal and the first inverse logic signal.
Abstract:
Systems for displaying images are provided. A representative system incorporates a display device that includes a data line operative to provide display signals and sweep signals; a scan line operative to provide scan reset signals; a first capacitor having a first end coupled to the data line for storing charges from the signal line; a first inversion unit having an input end coupled to a second end of the first capacitor, a first supply end coupled to a first voltage source, a second supply end coupled to a second voltage source larger than the first voltage, and an output end; a first reset switch having a first end coupled between the second end of the first capacitor and the input end of the first inversion unit, a second end coupled to the output end of the first inversion unit, and a control end coupled to the scan line; a driving TFT having a control end coupled to the output end of the first inversion unit; and an illuminating unit coupled between a first end of the driving TFT and a third voltage source larger than or equal to the first voltage source.
Abstract:
Architecture for transmitting a video signal and an control clock signal between an ASIC and a panel in a display is introduced. Two dummy shift registers (DSRs) and switches are used for sending out the control clock signal to an ASIC. The ASIC compares the control clock signal sent out from the DSR with the video signals desired to be sent to a display panel. Time difference between the control clock signal and the video signals is obtained by the ASIC and the video signals sent out from the ASIC are delayed with the time difference, in order to be synchronized with a shift pulse generated by operation of a shift register in the display.
Abstract:
A system for providing conducting pads of a display panel has a base layer on a substrate, a first insulator on the base layer having a plurality of grooves, a second conductive layer inside the grooves, and a patterned third conductive layer covering the second conductive layer. The first insulator serves as a barricade for fixing the second conductive layer in the grooves.
Abstract:
A representative device comprises a plurality of pixel units configured for use in a vertical alignment liquid crystal display, wherein a first of the pixel units comprises a first substrate, a second substrate and liquid crystal material. The first substrate comprises a pixel layer thereon, wherein the pixel layer comprises a thin film transistor and a pixel electrode, and the pixel electrode in the first of the pixel units has first openings therein. The second substrate comprises a common electrode thereon, wherein the common electrode has second openings therein, and the second openings and the first openings are arranged in an overlying and cross-over relationship with respect to each other. The liquid crystal layer is between the first and second substrates.