公开(公告)号：US20250067804A1

公开(公告)日：2025-02-27

申请号：US18946120

申请日：2024-11-13

Applicant: ADVANTEST CORPORATION

Inventor： Matthias SAUER ,  Olaf PÖPPE

IPC: G01R31/3183 ,  G01R31/319

Abstract: An automated test equipment comprises a main test flow control configured to operate a test flow in multiple device communication units and/or to provide the trigger configuration information to a local compute unit. The automated test equipment further comprises a device communication unit comprising a trigger generation unit configured to generate a trigger signal. The trigger generation unit further configured to extract payload data from a protocol-based data stream received from the device under test, and to generate the trigger signal in response to the extracted payload data or in response to one or more protocol events. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

公开(公告)号：US20250027982A1

公开(公告)日：2025-01-23

申请号：US18355395

申请日：2023-07-19

Applicant: ADVANTEST CORPORATION

Inventor： Yang SHANG ,  Masaichi HASHIMOTO ,  Makoto SHINOHARA

IPC: G01R31/11

Abstract: A method, apparatus, and/or system for soft defects modeling of measurements using time-domain reflectometry. Electro-Optic Sampling based Time-Domain Reflectometry (EOS-TDR) may quickly detect soft defects in a chip under test. For example, EOS-TDR may detect soft defects in each pin from a trace-structure point at a relatively high resolution. To interpret the results in a time sensitive manner, a reference model for chips may be established from chips that are known to have met the expected quality standards. Through automated analysis of the features of the device under test waveform, soft defects of a chip may be detected that would be otherwise undetectable under time constraints, temperature variations, applied current variations, applied voltage variations, vibration variations, moisture variations, or any other kind of possible variation.

公开(公告)号：US12146896B2

公开(公告)日：2024-11-19

申请号：US17202382

申请日：2021-03-16

Applicant: ADVANTEST CORPORATION

Inventor： Yuji Sakai ,  Hajime Sugimura

IPC: G01R1/067 ,  G01R31/28 ,  G06N20/00

Abstract: There is provided an analysis apparatus including: an acquisition unit configured to acquire a plurality of measured values obtained by measuring a device under measurement; a machine learning unit configured to use the plurality of measured values to learn, by machine learning, a model of a position-dependent component that depends on a measured position in the device under measurement; and an analysis unit configured to separate, from the plurality of measured values, the position-dependent component which is calculated by using the model learned by the machine learning unit. Further, there is provided an analysis method. Further, there is provided a recording medium having recorded thereon an analysis program.

公开(公告)号：US12135352B2

公开(公告)日：2024-11-05

申请号：US17219521

申请日：2021-03-31

Applicant: Advantest Corporation

Inventor： Marilyn Kushnick ,  Duane Champoux

IPC: G01R31/317 ,  G06F7/58

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments enable efficient and effective random generation of test input information. In one embodiment a method includes accessing a plurality of data values to write to a DUT, generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values, wherein assignments of a particular address to different respective ones of the data values are randomly repeatable; and directing writing of the data values to the DUT in accordance with the plurality of addresses that are randomly generated and randomly repeated. The generating a plurality of addresses randomly can include normalization. Generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values can include performing a confirmation check. The confirmation check can include checking if the addresses within proper parameters.

公开(公告)号：US12079098B2

公开(公告)日：2024-09-03

申请号：US17135790

申请日：2020-12-28

Applicant: Advantest Corporation

Inventor： Mei-Mei Su ,  Eddy Wayne Chow ,  Edmundo De La Puente

IPC: G06F11/273 ,  G01R31/317 ,  G06F13/42

CPC classification number: G06F11/2736 ,  G01R31/31724 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0028

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

公开(公告)号：US20240290741A1

公开(公告)日：2024-08-29

申请号：US18481203

申请日：2023-10-04

Applicant: ADVANTEST CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

Inventor： Shinji SUGATANI ,  Masaki TAKAKUWA ,  Shuji UEHARA ,  Takayuki OHBA

IPC: H01L23/00 ,  H01L21/683

CPC classification number: H01L24/32 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/30 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68363 ,  H01L2224/2732 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/8384 ,  H01L2224/97 ,  H01L2924/15151

Abstract: A manufacturing method of a semiconductor apparatus in which a semiconductor chip is joined to a target object, the manufacturing method including forming, in a joining region between the semiconductor chip and the target object where the semiconductor chip and the target object should be joined to each other, a plurality of metal paste patterns with a gap being provided in at least a part along a thickness direction between one another, and joining the semiconductor chip and the target object by sintering the plurality of metal paste patterns sandwiched between the semiconductor chip and the target object in a state where the gap exists between one another.

公开(公告)号：US20240234352A9

公开(公告)日：2024-07-11

申请号：US18450435

申请日：2023-08-16

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Norio CHUJO ,  Koji SAKUI ,  Tadashi FUKUDA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

公开(公告)号：US20240227208A9

公开(公告)日：2024-07-11

申请号：US18379063

申请日：2023-10-11

Applicant: ADVANTEST CORPORATION

Inventor： Patrick Sherman ,  Don Wagner ,  Moritoshi Akiya

IPC: B25J15/04 ,  B25J15/06 ,  B65G47/91

CPC classification number: B25J15/0441 ,  B25J15/0683 ,  B65G47/91

Abstract: Embodiments of the present invention provide a magnetically retained replaceable contact plate assembly. The magnetically retained replaceable contact plate assembly includes a contact chuck interface. The contact chuck is configured to physically mate with a device under test (DUT). The magnetically retained replaceable contact plate assembly also includes a DUT layout unit interface (DLU). The DLU is configured to couple to multiple magnetically retained replaceable contact plate assemblies and to a semiconductor handler unit. The DLU is configured to move DUTs within a test environment, and the magnetically retained replaceable contact plate assembly is configured to magnetically attach to said DLU.

公开(公告)号：US20240223179A1

公开(公告)日：2024-07-04

申请号：US18558285

申请日：2022-04-28

Applicant: ADVANTEST Corporation

Inventor： Kiyotaka Kasahara

IPC: H03K17/082 ,  G01R1/20 ,  H03K17/08

CPC classification number: H03K17/0822 ,  G01R1/203 ,  H03K2017/0806

Abstract: A protective circuit that protects a semiconductor switch includes a group of terminals consisting of either one or more input terminals and two or more output terminals, or one or more output terminals and two or more input terminals, a first resistive circuit, connected to one of the terminals, comprising a resistor having a first temperature coefficient of resistance; and a second resistive circuit, connected to another one of the terminals, comprising a resistor having a second temperature coefficient of resistance different in temperature characteristics from the first temperature coefficient of resistance. The protective circuit is electrically connected to a control terminal of the semiconductor switch, and shuts off a passing current of the semiconductor switch when a temperature of the semiconductor switch is equal to or higher than a current shut-off temperature.

公开(公告)号：US20240176721A1

公开(公告)日：2024-05-30

申请号：US18128931

申请日：2023-03-30

Applicant: ADVANTEST CORPORATION

Inventor： Chi Yuan ,  Srdjan Malisic

IPC: G06F11/34 ,  G06F11/07

CPC classification number: G06F11/3476 ,  G06F11/0787

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.