公开(公告)号：US08773831B2

公开(公告)日：2014-07-08

申请号：US13495797

申请日：2012-06-13

申请人： Akinobu Onishi ,  Yasuhiro Hinokuma ,  Kazuyuki Kobayashi ,  Kengo Murase

发明人： Akinobu Onishi ,  Yasuhiro Hinokuma ,  Kazuyuki Kobayashi ,  Kengo Murase

IPC分类号： H02H3/20

CPC分类号： H03F3/45188

摘要： A semiconductor integrated circuit that is efficiently reduced in a noise level is offered. P-channel type MOS transistors M1 and M2 serving as differential input transistors have a thin gate oxide film in order to reduce the noise level. A protection circuit to protect the P-channel type MOS transistors M1 and M2 from overvoltage is formed including P-channel type MOS transistors M3 and M4. The P-channel type MOS transistor M3 is a first protection transistor to protect the P-channel type MOS transistor M1 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M1. The P-channel type MOS transistor M4 is a second protection transistor to protect the P-channel type MOS transistor M2 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M2.

摘要翻译： 提供了可以有效降低噪声水平的半导体集成电路。 用作差分输入晶体管的P沟道型MOS晶体管M1和M2具有薄的栅极氧化膜，以便降低噪声水平。 形成保护P沟道型MOS晶体管M1和M2免受过电压的保护电路，其包括P沟道型MOS晶体管M3和M4。 P沟道型MOS晶体管M3是用于保护P沟道型MOS晶体管M1免受过电压的第一保护晶体管，并且连接到P沟道型MOS晶体管M1的漏极。 P沟道型MOS晶体管M4是用于保护P沟道型MOS晶体管M2免受过电压的第二保护晶体管，并且连接到P沟道型MOS晶体管M2的漏极。

公开(公告)号：US20120320482A1

公开(公告)日：2012-12-20

申请号：US13495797

申请日：2012-06-13

申请人： Akinobu ONISHI ,  Yasuhiro Hinokuma ,  Kazuyuki Kobayashi ,  Kengo Murase

发明人： Akinobu ONISHI ,  Yasuhiro Hinokuma ,  Kazuyuki Kobayashi ,  Kengo Murase

IPC分类号： H02H3/20

CPC分类号： H03F3/45188

摘要： A semiconductor integrated circuit that is efficiently reduced in a noise level is offered. P-channel type MOS transistors M1 and M2 serving as differential input transistors have a thin gate oxide film in order to reduce the noise level. A protection circuit to protect the P-channel type MOS transistors M1 and M2 from overvoltage is formed including P-channel type MOS transistors M3 and M4. The P-channel type MOS transistor M3 is a first protection transistor to protect the P-channel type MOS transistor M1 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M1. The P-channel type MOS transistor M4 is a second protection transistor to protect the P-channel type MOS transistor M2 from overvoltage, and is connected to a drain of the P-channel type MOS transistor M2.

摘要翻译： 提供了可以有效降低噪声水平的半导体集成电路。 用作差分输入晶体管的P沟道型MOS晶体管M1和M2具有薄的栅极氧化膜，以便降低噪声水平。 形成保护P沟道型MOS晶体管M1和M2免受过电压的保护电路，其包括P沟道型MOS晶体管M3和M4。 P沟道型MOS晶体管M3是用于保护P沟道型MOS晶体管M1免受过电压的第一保护晶体管，并且连接到P沟道型MOS晶体管M1的漏极。 P沟道型MOS晶体管M4是用于保护P沟道型MOS晶体管M2免受过电压的第二保护晶体管，并且连接到P沟道型MOS晶体管M2的漏极。

公开(公告)号：US07358813B2

公开(公告)日：2008-04-15

申请号：US11531207

申请日：2006-09-12

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/264 ,  H03F2200/366 ,  H03F2203/45008 ,  H03F2203/45012 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45088 ,  H03F2203/45471 ,  H03F2203/45508 ,  H03F2203/45551 ,  H03F2203/45616 ,  H03F2203/45642

摘要： Disclosed is a differential operational amplifier that outputs first and second output voltages corresponding to first and second input voltages, the amplifier comprising a differential circuit that operates depending on the first and second input voltages; a control voltage generation circuit that generates a control voltage for making an intermediate voltage of the first and second output voltages become a predetermined reference voltage; a variable current generation circuit that is connected serially to the differential circuit to generate a variable current corresponding to the control voltage; and a constant current generation circuit that is connected in parallel with the variable current generation circuit to generate a constant current, control being performed with the variable current and the constant current such that the intermediate voltage turns to the reference voltage.

摘要翻译： 公开了一种差分运算放大器，其输出对应于第一和第二输入电压的第一和第二输出电压，该放大器包括根据第一和第二输入电压工作的差分电路; 生成用于使所述第一和第二输出电压的中间电压成为规定的基准电压的控制电压的控制电压产生电路; 可变电流产生电路，其串联连接到所述差分电路以产生对应于所述控制电压的可变电流; 以及与可变电流产生电路并联连接以产生恒定电流的恒流产生电路，用可变电流和恒定电流进行控制，使得中间电压变为参考电压。

公开(公告)号：US20070057727A1

公开(公告)日：2007-03-15

申请号：US11531207

申请日：2006-09-12

申请人： Akinobu ONISHI

发明人： Akinobu ONISHI

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/264 ,  H03F2200/366 ,  H03F2203/45008 ,  H03F2203/45012 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45088 ,  H03F2203/45471 ,  H03F2203/45508 ,  H03F2203/45551 ,  H03F2203/45616 ,  H03F2203/45642

摘要： Disclosed is a differential operational amplifier that outputs first and second output voltages corresponding to first and second input voltages, the amplifier comprising a differential circuit that operates depending on the first and second input voltages; a control voltage generation circuit that generates a control voltage for making an intermediate voltage of the first and second output voltages become a predetermined reference voltage; a variable current generation circuit that is connected serially to the differential circuit to generate a variable current corresponding to the control voltage; and a constant current generation circuit that is connected in parallel with the variable current generation circuit to generate a constant current, control being performed with the variable current and the constant current such that the intermediate voltage turns to the reference voltage.

摘要翻译： 公开了一种差分运算放大器，其输出对应于第一和第二输入电压的第一和第二输出电压，该放大器包括根据第一和第二输入电压工作的差分电路; 生成用于使所述第一和第二输出电压的中间电压成为规定的基准电压的控制电压的控制电压产生电路; 可变电流产生电路，其串联连接到所述差分电路以产生对应于所述控制电压的可变电流; 以及与可变电流产生电路并联连接以产生恒定电流的恒流产生电路，以可变电流和恒定电流进行控制，使得中间电压变为参考电压。

公开(公告)号：US20110150243A1

公开(公告)日：2011-06-23

申请号：US12972303

申请日：2010-12-17

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H04R3/00 ,  G05F1/10

CPC分类号： H02M3/07 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45526 ,  H03F2203/45568 ,  H03F2203/45571

摘要： A charging circuit comprising: a charge-pump circuit configured to generates a boosted voltage obtained by boosting an input voltage at each time interval shorter in accordance with an increase of a frequency of an input clock signal; an integrating circuit configured to integrate the boosted voltage to apply the integrated boosted voltage to a capacitor; and a clock signal output circuit configured to output a second clock signal higher in frequency than a first clock signal to the charge-pump circuit as the clock signal, and thereafter output the first clock signal to the charge-pump circuit as the clock signal, in order that a charge voltage of the capacitor reaches a predetermined voltage level in a time shorter than a time in which the charge voltage of the capacitor reaches the predetermined voltage level when the first clock signal is input to the charge-pump circuit as the clock signal.

摘要翻译： 一种充电电路，包括：电荷泵电路，被配置为根据输入时钟信号的频率的增加，产生通过在每个时间间隔升高输入电压而获得的升压电压; 积分电路，被配置为积分升压电压以将积分升压电压施加到电容器; 以及时钟信号输出电路，被配置为将作为时钟信号的频率比第一时钟信号高的第二时钟信号输出到电荷泵电路，然后将第一时钟信号作为时钟信号输出到电荷泵电路， 为了在第一时钟信号被输入到电荷泵电路作为时钟时，电容器的充电电压在比电容器的充电电压达到预定电压电平的时间短的时间内达到预定的电压电平 信号。

公开(公告)号：US20110150239A1

公开(公告)日：2011-06-23

申请号：US12972317

申请日：2010-12-17

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H04B15/00 ,  H03M1/12 ,  H03M3/02

CPC分类号： H03M3/322 ,  H03M1/089 ,  H03M1/12 ,  H03M3/43 ,  H03M3/456

摘要： A signal processing circuit includes: an AD converter configured to quantize an input signal, whose amplitude changes in accordance with temperature, within a set voltage range and convert the quantized input signal into a digital signal; and a setting circuit configured to set the voltage range so as to be wider when the input signal is greater in amplitude in accordance with the temperature and so as to be narrower when the input signal is smaller in amplitude in accordance with the temperature.

摘要翻译： 信号处理电路包括：AD转换器，被配置为在设定的电压范围内对其幅度根据温度变化的输入信号进行量化，并将量化的输入信号转换为数字信号; 以及设定电路，其被配置为当所述输入信号根据所述温度的幅度较大时将所述电压范围设定得更宽，并且当所述输入信号的温度根据振幅较小时，所述设定电路被设定得较窄。

公开(公告)号：US20070171118A1

公开(公告)日：2007-07-26

申请号：US11462690

申请日：2006-08-04

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H03M1/12

CPC分类号： H03M3/356 ,  H03M3/43 ,  H03M3/456

摘要： A switch control circuit turns on/off second and third switches, while turning off/on first and fourth switches, in a complementary manner in an integrator constituted by using a switched capacitor including the first to fourth switches and, where the first and fourth switches are turned off and the second and third switches are turned on, the switch control circuit turns on the second switch before turning off the fourth switch.

摘要翻译： 开关控制电路在通过使用包括第一至第四开关的开关电容器构成的积分器中以互补方式断开/关闭第二和第四开关而导通/关闭第二和第三开关，并且其中第一和第四开关 断开，第二和第三开关导通，开关控制电路在关闭第四开关之前接通第二开关。

公开(公告)号：US09014398B2

公开(公告)日：2015-04-21

申请号：US12972303

申请日：2010-12-17

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H04R3/00 ,  H02M3/07 ,  H03F3/187 ,  H03F3/45

CPC分类号： H02M3/07 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45526 ,  H03F2203/45568 ,  H03F2203/45571

摘要： A charging circuit includes a charge pump circuit, an integrating circuit, and a clock signal output circuit. The charge pump circuit generates a boosted voltage by boosting an input voltage at a rate in synchronization with an input clock signal. The integrating circuit is configured to integrate the boosted voltage to apply the integrated boosted voltage to a boost capacitor. The clock signal output circuit is configured to output a second clock signal that is higher in frequency than a first clock signal to the charge pump circuit as the clock signal for a predetermined period of time upon start up, and thereafter output the first clock signal to the charge pump circuit as the clock signal.

摘要翻译： 充电电路包括电荷泵电路，积分电路和时钟信号输出电路。 电荷泵电路通过以与输入时钟信号同步的速率升高输入电压来产生升压电压。 集成电路被配置为集成升压电压以将积分升压电压施加到升压电容器。 时钟信号输出电路被配置为在启动时将与第一时钟信号相比频率高于第一时钟信号的第二时钟信号作为时钟信号输出到电荷泵电路预定时间段，然后将第一时钟信号输出到 电荷泵电路作为时钟信号。

公开(公告)号：US08693707B2

公开(公告)日：2014-04-08

申请号：US12972317

申请日：2010-12-17

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H04R3/00

CPC分类号： H03M3/322 ,  H03M1/089 ,  H03M1/12 ,  H03M3/43 ,  H03M3/456

摘要： A signal processing circuit includes: an AD converter configured to quantize an input signal, whose amplitude changes in accordance with temperature, within a set voltage range and convert the quantized input signal into a digital signal; and a setting circuit configured to set the voltage range so as to be wider when the input signal is greater in amplitude in accordance with the temperature and so as to be narrower when the input signal is smaller in amplitude in accordance with the temperature.

摘要翻译： 信号处理电路包括：AD转换器，被配置为在设定的电压范围内对其幅度根据温度变化的输入信号进行量化，并将量化的输入信号转换为数字信号; 以及设定电路，其被配置为当所述输入信号根据所述温度的幅度较大时将所述电压范围设定得更宽，并且当所述输入信号的温度根据振幅较小时，所述设定电路被设定得较窄。

公开(公告)号：US08374363B2

公开(公告)日：2013-02-12

申请号：US12728643

申请日：2010-03-22

申请人： Akinobu Onishi

发明人： Akinobu Onishi

IPC分类号： H04R3/00

CPC分类号： H03F3/187 ,  H01L27/0811 ,  H01L29/94 ,  H03F1/3211 ,  H03F1/34 ,  H03F3/181 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45136 ,  H03F2203/45526 ,  H03F2203/45528 ,  H04R3/00 ,  H04R19/016

摘要： In an amplifier circuit of a capacitor microphone, when a too high input signal from the capacitor microphone is inputted, the levels of output signals of the amplifier circuit are limited. A first feedback capacitor of an operational amplifier is formed using a changeable capacitance type MOS capacitor element, and has a characteristic of increasing the capacitance value CAf1 according to the amplitude of an input signal generated by a capacitor increases. Therefore, CAf (=CAf1+CAF2) increases according to the amplitude of the input signal increases, and accordingly the gain of the operational amplifier decreases, thereby limiting the output signals of the operational amplifier. This realizes the appropriate limitation of the output signals of the operational amplifier, even when the amplitude of the input signal becomes too high.

摘要翻译： 在电容麦克风的放大器电路中，当输入来自电容麦克风的输入信号太高时，放大器电路的输出信号的电平受到限制。 使用可变电容型MOS电容器元件形成运算放大器的第一反馈电容器，并且具有根据由电容器生成的输入信号的幅度增加的电容值CAf1增加的特性。 因此，CAf（= CAf1 + CAF2）根据输入信号的幅度而增加，因此运算放大器的增益减小，从而限制运算放大器的输出信号。 这实现了运算放大器的输出信号的适当限制，即使当输入信号的幅度变得过高时也是如此。