公开(公告)号：US20150270177A1

公开(公告)日：2015-09-24

申请号：US14592842

申请日：2015-01-08

申请人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

发明人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC分类号： H01L21/8238 ,  H01L29/40 ,  H01L21/324 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

公开(公告)号：US20160315087A1

公开(公告)日：2016-10-27

申请号：US15069920

申请日：2016-03-14

申请人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

发明人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC分类号： H01L27/092 ,  H01L29/43 ,  H01L29/49

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

公开(公告)号：US09287181B2

公开(公告)日：2016-03-15

申请号：US14592842

申请日：2015-01-08

申请人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

发明人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

公开(公告)号：US20130249019A1

公开(公告)日：2013-09-26

申请号：US13425218

申请日：2012-03-20

申请人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

发明人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

IPC分类号： H01L29/78 ,  H01L21/285

CPC分类号： H01L29/7851 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/7845 ,  H01L29/785

摘要： A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

公开(公告)号：US08703556B2

公开(公告)日：2014-04-22

申请号：US13599393

申请日：2012-08-30

申请人： Andrew Joseph Kelly ,  Po-Ruwe Tzng ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

发明人： Andrew Joseph Kelly ,  Po-Ruwe Tzng ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/7851

摘要： A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.

摘要翻译： 通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底和衬底上的翅片结构。 在前体中翅片结构的侧壁上形成侧壁间隔物。 翅片结构的一部分被凹入以形成具有侧壁间隔件作为其上部的凹陷沟槽。 在凹槽中外延生长半导体，并在凹陷沟槽上方持续生长以形成外延结构。

公开(公告)号：US09553094B2

公开(公告)日：2017-01-24

申请号：US15069920

申请日：2016-03-14

申请人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

发明人： Wei-Hsiung Tseng ,  Ju-Youn Kim ,  Seok-Jun Won ,  Jong-Ho Lee ,  Hye-Lan Lee ,  Yong-Ho Ha

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/43

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

公开(公告)号：US08872284B2

公开(公告)日：2014-10-28

申请号：US13425218

申请日：2012-03-20

申请人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

发明人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/7845 ,  H01L29/785

摘要： A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

摘要翻译： 提供了一种用于鳍式场效应晶体管（FinFET）器件的栅极应力器。 闸应力器包括地板，第一应力侧壁和第二应力侧壁。 地板形成在栅极层的第一部分上。 栅极层设置在浅沟槽隔离（STI）区域的上方。 第一应力侧壁形成在栅极层的第二部分上。 栅极层的第二部分设置在散热片的侧壁上。 第二应力侧壁形成在栅极层的第三部分上。 栅极层的第三部分设置在与散热片间隔开的结构的侧壁上。 第一应力侧壁和第二应力侧壁不超过翅片的高度。