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    Non-volatile memory device and a method of programming such device
    1.
    发明授权
    Non-volatile memory device and a method of programming such device 有权
    非易失性存储器件和这种器件的编程方法

    公开(公告)号：US08804429B2

    公开(公告)日：2014-08-12

    申请号：US13315213

    申请日：2011-12-08

    申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    IPC分类号： G11C16/04 ,  G11C7/00

    CPC分类号： G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

    摘要： A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

    摘要翻译： 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

    Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving
    2.
    发明申请
    Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving 有权
    具有省电的混合电压非易失性存储器集成电路

    公开(公告)号：US20130107632A1

    公开(公告)日：2013-05-02

    申请号：US13286969

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G11C5/14 ,  G05F3/02

    CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.

    摘要翻译： 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 检测来自第二管芯焊盘的电流的电路在集成电路管芯中。 开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

    Low Voltage, Low Power Bandgap Circuit
    3.
    发明申请
    Low Voltage, Low Power Bandgap Circuit 有权
    低电压，低功耗带隙电路

    公开(公告)号：US20130106391A1

    公开(公告)日：2013-05-02

    申请号：US13286843

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G05F3/16

    CPC分类号： G05F3/30

    摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.

    摘要翻译： 用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。 电流镜电路具有至少两个平行电流路径。 每个电流路径由运算放大器的输出控制。 电流路径之一耦合到运算放大器的两个输入之一。 电阻分压电路连接到另一个电流通路。 电阻分压电路提供电路的带隙电压。

    Low voltage, low power bandgap circuit
    6.
    发明授权
    Low voltage, low power bandgap circuit 有权
    低电压，低功耗带隙电路

    公开(公告)号：US09092044B2

    公开(公告)日：2015-07-28

    申请号：US13286843

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G05F3/02 ,  G05F3/30

    CPC分类号： G05F3/30

    摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.

    摘要翻译： 用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。 电流镜电路具有至少两个平行电流路径。 每个电流路径由运算放大器的输出控制。 电流路径之一耦合到运算放大器的两个输入之一。 电阻分压电路连接到另一个电流通路。 电阻分压电路提供电路的带隙电压。

    Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming
    7.
    发明申请
    Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming 有权
    非易失性存储器阵列及使用相同的分数字编程方法

    公开(公告)号：US20140104965A1

    公开(公告)日：2014-04-17

    申请号：US13652447

    申请日：2012-10-15

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

    摘要： A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

    摘要翻译： 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

    Mixed voltage non-volatile memory integrated circuit with power saving
    8.
    发明授权
    Mixed voltage non-volatile memory integrated circuit with power saving 有权
    混合电压非易失性存储器集成电路，省电

    公开(公告)号：US08705282B2

    公开(公告)日：2014-04-22

    申请号：US13286969

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.

    摘要翻译： 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 检测来自第二管芯焊盘的电流的电路在集成电路管芯中。 开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

    CHARGE PUMP SYSTEMS AND METHODS
    9.
    发明申请
    CHARGE PUMP SYSTEMS AND METHODS 有权
    充电泵系统和方法

    公开(公告)号：US20110169558A1

    公开(公告)日：2011-07-14

    申请号：US13070405

    申请日：2011-03-23

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    IPC分类号： G05F1/10

    CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

    摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

    摘要翻译： 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。