公开(公告)号：US20050283561A1

公开(公告)日：2005-12-22

申请号：US10873779

申请日：2004-06-21

申请人： John Lee ,  Aniruddha Joshi ,  Geetani Edirisooriya

发明人： John Lee ,  Aniruddha Joshi ,  Geetani Edirisooriya

IPC分类号： G06F1/20 ,  G06F1/32 ,  G06F13/40

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3209 ,  Y02D10/126

摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises detecting a temperature event in a processor and modifying bus frequency of a bus coupled to the processor in response to the temperature event.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括检测处理器中的温度事件并且响应于温度事件修改耦合到处理器的总线的总线频率。

公开(公告)号：US20060075177A1

公开(公告)日：2006-04-06

申请号：US11263038

申请日：2005-10-31

申请人： John Lee ,  Atul Kwatra ,  Aniruddha Joshi

发明人： John Lee ,  Atul Kwatra ,  Aniruddha Joshi

IPC分类号： G06F13/14

CPC分类号： G06F13/4004 ,  G06F2213/0024

摘要： Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

摘要翻译： 提供使用外部微控制器访问计算机系统芯片组上的内部配置寄存器。 可以从外部微控制器接收包括寄存器地址的SMB配置读取命令。 可以从总线仲裁器请求访问内部总线。 如果内部总线访问被授予，SMB配置读取命令可以使用内部总线转发到包括所识别的寄存器地址的设备。 响应于SMB配置读命令，可以接收来自设备的配置寄存器值。 配置寄存器值可以转发到外部微控制器。

公开(公告)号：US06514825B1

公开(公告)日：2003-02-04

申请号：US09606778

申请日：2000-06-28

申请人： Sandeep D'Souza ,  Li-Ming Hwang ,  Aniruddha Joshi ,  Suryanarayana Shivakumar Bhattacharya

发明人： Sandeep D'Souza ,  Li-Ming Hwang ,  Aniruddha Joshi ,  Suryanarayana Shivakumar Bhattacharya

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823857 ,  H01L29/518

摘要： An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

摘要翻译： 用于MOSFET器件的改进的栅极结构表现出降低的1 / f噪声或“闪烁噪声”的水平，同时保持硼渗透到MOSFET器件的衬底中的控制。 用于MOSFET器件的栅极结构包括栅极电极和栅极氧化物层，其中在栅极氧化物层氧化之前氮被选择性地注入到栅极氧化物/器件衬底界面中。 选择性地注入氮气，使得氮被注入到薄的栅极氧化物区域并从厚的栅极氧化物区域掩蔽，从而在1 / f噪声由于氮的选择性注入而降低时实现控制硼渗透的益处 。

公开(公告)号：US20100152594A1

公开(公告)日：2010-06-17

申请号：US12733153

申请日：2008-08-07

申请人： Ashok Bhat ,  Aniruddha Joshi ,  Anand Kulkarni ,  Bhaskar Kulkarni ,  Valadi Jayaraman ,  Sharat Chandran

发明人： Ashok Bhat ,  Aniruddha Joshi ,  Anand Kulkarni ,  Bhaskar Kulkarni ,  Valadi Jayaraman ,  Sharat Chandran

IPC分类号： A61B5/0245

CPC分类号： A61B5/021 ,  A61B5/02116 ,  A61B5/4854 ,  A61B5/6824 ,  A61B5/6844 ,  A61B5/6886 ,  A61B5/7203 ,  A61B5/726 ,  A61B2560/045 ,  A61B2562/0247 ,  A61B2562/043 ,  A61B2562/046 ,  A61B2562/164

摘要： The present invention discloses the procedure for obtaining complete spectrum of the Nadi pulses, as a time series and capable of detecting the major types and the subtypes of the Nadi pulses. The device of this invention involves three diaphragm elements equipped with strain gauge, three transmitters cum amplifiers, and a digitizer for quantifying analog signal. The system acquires the data with 12-bit accuracy with practically no electronic and/or external interfering noise. The pertaining proofs are given which clearly shows the capability of delivering the accurate spectrums, with repeatability of the pulses from the invented system. ‘Nadi-Nidan’ is a prominent method in Ayurveda (Ayurveda is a Sanskrit word derived from ‘Ayus’ and ‘vid’, meaning life and knowledge respectively. It is a holistic science encompassing mental, physical and spiritual health), which is known to dictate all the salient features of a human body. Nadi-Nidan is a specialty of ‘Vaidyas’ (Ayurvedic physicians) and hence the present system would enable the diagnosis accurately, quantitatively and independent of any human errors.

摘要翻译： 本发明公开了用于获得Nadi脉冲的完整光谱作为时间序列并且能够检测Nadi脉冲的主要类型和亚型的过程。 本发明的装置包括配有应变计的三个隔膜元件，三个发射器和放大器以及用于量化模拟信号的数字化仪。 系统以12位精度获取数据，几乎没有电子和/或外部干扰噪声。 给出了相关证明，其清楚地显示了传递精确谱的能力，并且具有来自本发明系统的脉冲的可重复性。 “N adi an an an an known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known known 规定人体的所有显着特征。 Nadi-Nidan是“Vaidyas”（阿育吠陀医师）的专长，因此本系统能使诊断准确，定量和独立于任何人为错误。

公开(公告)号：US07035262B1

公开(公告)日：2006-04-25

申请号：US10029188

申请日：2001-12-19

申请人： Aniruddha Joshi

发明人： Aniruddha Joshi

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L1/22 ,  H04J3/14 ,  H04J3/1617 ,  H04J2203/006 ,  H04J2203/0073 ,  H04J2203/0089 ,  Y10S370/907

摘要： A system and method are disclosed for using standard issue synchronous optical network (SONET) framers to comply with current automatic protection system (APS) standards. Each standard framer includes its own section, line, and path layer termination. The working set of lines and protection set of lines of the APS system are switched after the path layer rather than before. A firmware solution allows for a proper use of various error indication signals.

摘要翻译： 公开了一种使用标准问题同步光网络（SONET）成帧器来符合当前自动保护系统（APS）标准的系统和方法。 每个标准成帧器都包含自己的部分，行和路径层终止。 APS系统的线路和线路的工作集在路径层之后而不是之前被切换。 固件解决方案可以正确使用各种错误指示信号。

公开(公告)号：US20050193288A1

公开(公告)日：2005-09-01

申请号：US10779140

申请日：2004-02-13

申请人： Aniruddha Joshi ,  John Lee ,  Geetani Edirisooriya

发明人： Aniruddha Joshi ,  John Lee ,  Geetani Edirisooriya

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0793 ,  G06F11/0745 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/079

摘要： In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

摘要翻译： 在一些实施例中，描述了用于在奇偶校验错误检测之后维持数据完整性的方法和装置。 在一个实施例中，该方法包括响应于奇偶校验错误的检测而阻塞总线事务。 一旦暂停总线事务，根据存储的关于检测到的奇偶校验错误的错误总线事务的事务信息，调用奇偶校验错误处理程序来执行奇偶校验错误恢复。 在一个实施例中，所存储的信息包括导致错误的总线主机，以及与被断言奇偶校验错误的损坏数据相关联的地址。 在一个实施例中，执行数据记录以跟踪与错误总线事务相关联的总线主控器，以便能够识别有问题的或旧的硬件设备。 其他实施例被描述和权利要求。

公开(公告)号：US06653679B2

公开(公告)日：2003-11-25

申请号：US10015411

申请日：2001-12-11

申请人： Sandeep D'Souza ,  Li-Ming Hwang ,  Aniruddha Joshi ,  Suryanarayana Shivakumar Bhattacharya

发明人： Sandeep D'Souza ,  Li-Ming Hwang ,  Aniruddha Joshi ,  Suryanarayana Shivakumar Bhattacharya

IPC分类号： H01L2976

CPC分类号： H01L21/28202 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823857 ,  H01L29/518

摘要： An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

公开(公告)号：US20060265541A1

公开(公告)日：2006-11-23

申请号：US11462264

申请日：2006-08-03

申请人： Jennifer Wang ,  Aniruddha Joshi ,  Peter Munguia

发明人： Jennifer Wang ,  Aniruddha Joshi ,  Peter Munguia

IPC分类号： G06F13/36

CPC分类号： G06F13/4004

摘要： A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

摘要翻译： 监视计算设备性能的系统包括与第一组设备进行接口的第一桥接器和与第二组设备接口的第二桥接器。 配置寄存器存储与第二组设备相关联的配置数据，并且可通过第二桥接器访问。 集线器接口允许数据从第一桥下游传输到第二桥，并且允许数据从第二桥上游传输到第一桥。 在第一和第二桥外部的控制器通过第二桥接器访问配置寄存器。 逻辑设备允许第二桥接器向控制器发送数据并从控制器接收数据。

公开(公告)号：US20050182886A1

公开(公告)日：2005-08-18

申请号：US10780372

申请日：2004-02-17

申请人： Geetani Edirisooriya ,  Aniruddha Joshi ,  John Lee

发明人： Geetani Edirisooriya ,  Aniruddha Joshi ,  John Lee

IPC分类号： G06F13/40 ,  G06F13/14

CPC分类号： G06F13/4027

摘要： Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

摘要翻译： 支持PCI桥中多功能PCI设备的方法和装置。 响应于由多功能PCI设备发出的各自的初始数据传送请求分配各自的预取缓冲器。 为每个预取缓冲区设置可编程缓冲区填充水印。 虽然对应于数据传输请求的一部分数据填充预取缓冲器，但是监视每个缓冲器的填充级别以确定其是否满足或超过其缓冲区填充水印。 响应于这种情况，多功能PCI设备连接到PCI桥，虚拟缓冲器被映射到预取缓冲器。 然后将预取缓冲区清空。 在随后的数据传输期间，每个预取缓冲区都被填满，PCI设备被连接，虚拟缓冲区被映射到已填充的缓冲区。 该过程一直持续到多功能PCI设备接收到与原始数据传送请求相对应的所有数据。

公开(公告)号：US06922741B2

公开(公告)日：2005-07-26

申请号：US10060336

申请日：2002-02-01

申请人： Robert Burton ,  Jennifer Wang ,  Aniruddha Joshi

发明人： Robert Burton ,  Jennifer Wang ,  Aniruddha Joshi

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

摘要翻译： 本发明的实施例为DMA控制器的每个通道提供状态寄存器。 状态寄存器可用于监视和记录在DMA数据传输期间发生的事件，包括超时和中断。