公开(公告)号：US20060097167A1

公开(公告)日：2006-05-11

申请号：US10972696

申请日：2004-10-25

Applicant: Anthony Domenicucci ,  Yun-Yu Wang

Inventor： Anthony Domenicucci ,  Yun-Yu Wang

IPC: G21K7/00

CPC classification number: H01J37/26 ,  G03H5/00 ,  H01J37/04 ,  H01J2237/0492 ,  H01J2237/1514 ,  H01J2237/2614

Abstract: A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident parallel beam, the initial virtual source positioned at a back focal plane of said first lens. A second lens is configured to form an intermediate virtual source with respect to the incident parallel beam, the position of said intermediate virtual source being dependent upon a focal length of the first lens and a focal length of the second lens. A third lens is configured to form a final virtual source with respect to the incident parallel beam, wherein the third lens has a focal length such that a front focal plane of the third lens lies beyond the position of the intermediate virtual source, with respect to a biprism location.

Abstract translation: 一种用于增强电子全息术配置的透射电子显微镜TEM系统的空间分辨率的方法。 在示例性实施例中，该方法包括配置第一透镜以相对于入射平行光束形成初始虚拟光源，初始虚拟光源位于所述第一透镜的后焦平面。 第二透镜被配置为相对于入射平行光束形成中间虚拟光源，所述中间虚拟光源的位置取决于第一透镜的焦距和第二透镜的焦距。 第三透镜被配置为相对于入射平行光束形成最终的虚拟光源，其中第三透镜具有焦距，使得第三透镜的前焦面超过中间虚拟光源的位置，相对于 双棱镜位置。

公开(公告)号：US20060081837A1

公开(公告)日：2006-04-20

申请号：US11293774

申请日：2005-12-02

Applicant: Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

Inventor： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

IPC: H01L31/109

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

公开(公告)号：US06475893B2

公开(公告)日：2002-11-05

申请号：US09822588

申请日：2001-03-30

Applicant: Kenneth J. Giewont ,  Yun Yu Wang ,  Russell Arndt ,  Craig Ransom ,  Judith Coffin ,  Anthony Domenicucci ,  Michael MacDonald ,  Brian E. Johnson

Inventor： Kenneth J. Giewont ,  Yun Yu Wang ,  Russell Arndt ,  Craig Ransom ,  Judith Coffin ,  Anthony Domenicucci ,  Michael MacDonald ,  Brian E. Johnson

IPC: H01L213205

CPC classification number: H01L21/02054 ,  H01L21/02063 ,  H01L21/31111 ,  H01L29/665

Abstract: A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.

Abstract translation: 公开了一种在选定区域上形成硅化物层的半导体材料的方法。 在本发明的一个示例性实施例中，该方法包括从所选择的区域去除氮化物和氮氧化物膜中的至少一种，从所选择的区域去除金属颗粒，从所选择的区域去除表面颗粒，从所选择的区域去除有机物， 并从所选择的区域去除氧化物层。

公开(公告)号：US20070128867A1

公开(公告)日：2007-06-07

申请号：US11672363

申请日：2007-02-07

Applicant: Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Wang ,  Kwong Wong

Inventor： Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Wang ,  Kwong Wong

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L21/28518 ,  H01L29/665

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.

Abstract translation: 本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。 第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。 第一热循环导致形成含非晶态金属的硅化物。 第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。 在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。 执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。 提供了一种金属硅化物，其厚度是自限制的。

公开(公告)号：US20070105350A1

公开(公告)日：2007-05-10

申请号：US11619040

申请日：2007-01-02

Applicant: Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

Inventor： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC: C30B1/00 ,  H01L21/20

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

Abstract translation: 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20080116483A1

公开(公告)日：2008-05-22

申请号：US12027561

申请日：2008-02-07

Applicant: Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Richard Murphy ,  Devendra Sadana

Inventor： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Richard Murphy ,  Devendra Sadana

IPC: H01L29/165

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

Abstract translation: 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

公开(公告)号：US20060057844A1

公开(公告)日：2006-03-16

申请号：US10711365

申请日：2004-09-14

Applicant: Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Yu Wang ,  Kwong Hon Wong

Inventor： Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Yu Wang ,  Kwong Hon Wong

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L29/665

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.

Abstract translation: 本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。 第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。 第一热循环导致形成含非晶态金属的硅化物。 第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。 在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。 执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。 提供了一种金属硅化物，其厚度是自限制的。

公开(公告)号：US20050208780A1

公开(公告)日：2005-09-22

申请号：US11029921

申请日：2005-01-05

Applicant: Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

Inventor： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC: C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/324 ,  H01L21/477 ,  H01L21/762 ,  H01L27/01

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract translation: 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

公开(公告)号：US20050003229A1

公开(公告)日：2005-01-06

申请号：US10610612

申请日：2003-07-01

Applicant: Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

Inventor： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/425 ,  B32B15/00

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

Abstract translation: 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20060065830A1

公开(公告)日：2006-03-30

申请号：US10711690

申请日：2004-09-30

Applicant: Thomas Bauer ,  Steven Boettcher ,  Anthony Domenicucci ,  John Gaudiello ,  Leon Kimball ,  Jeffrey McMurray ,  Yun-Yu Wang

Inventor： Thomas Bauer ,  Steven Boettcher ,  Anthony Domenicucci ,  John Gaudiello ,  Leon Kimball ,  Jeffrey McMurray ,  Yun-Yu Wang

IPC: G01N1/32 ,  G01N23/04

CPC classification number: G01N1/32 ,  G01N23/04 ,  H01J2237/2614

Abstract: A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.

Abstract translation: 制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入 。 抛光后，从样品中除去牺牲材料。