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    Programmable logic array integrated circuits
    2.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US5828229A

    公开(公告)日：1998-10-27

    申请号：US847004

    申请日：1997-05-01

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

    Variable depth and width memory device
    5.
    发明授权
    Variable depth and width memory device 失效
    可变深度和宽度的存储设备

    公开(公告)号：US5717901A

    公开(公告)日：1998-02-10

    申请号：US555109

    申请日：1995-11-08

    申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F12/00

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

    摘要翻译： 提供了可编程可变深度和宽度随机存取存储器电路。 存储器电路包含用于存储数据的存储单元的行和列。 行解码器用于寻址存储器单元的各行。 列地址电路接收列地址信号和宽度和深度选择信号。 列地址电路中的列解码器基于阵列的选定宽度来寻址RAM阵列的一列或多列存储单元。 列解码器的输出通过固定连接和一组可编程多路复用器的模式路由到存储器单元的适当列或列。 提供数据信号的数据输出线的数量由RAM阵列的选定宽度决定。 输出电路包含一组可编程解复用器和具有适于将数据信号从RAM阵列传递到选定数量的数据输出线的固定连接图案的路由阵列。

    Apparatus for serial reading and writing of random access memory arrays
    6.
    发明授权
    Apparatus for serial reading and writing of random access memory arrays 失效
    用于串行读取和写入随机存取存储器阵列的装置

    公开(公告)号：US5555214A

    公开(公告)日：1996-09-10

    申请号：US555110

    申请日：1995-11-08

    申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

    发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

    CPC分类号： G11C7/103 ,  G11C7/22

    摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.

    摘要翻译： 提供了串行读取和写入随机存取存储器阵列的方法。 尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。

    Apparatus for serial reading and writing of random access memory arrays
    7.
    再颁专利
    Apparatus for serial reading and writing of random access memory arrays 失效
    用于串行读取和写入随机存取存储器阵列的装置

    公开(公告)号：USRE37060E1

    公开(公告)日：2001-02-20

    申请号：US09010384

    申请日：1998-01-21

    申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

    发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang

    IPC分类号： G11C700

    CPC分类号： G11C7/103 ,  G11C7/22

    摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.

    摘要翻译： 提供了串行读取和写入随机存取存储器阵列的方法。 尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。