公开(公告)号：US20060097370A1

公开(公告)日：2006-05-11

申请号：US10970410

申请日：2004-10-21

申请人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

发明人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

IPC分类号： H01L23/02

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0203 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/0394 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronic assembly and system and method implementing the same are disclosed herein. The electronic assembly includes an IC carrier package having circuitry contained within a housing unit. The IC carrier package includes a connector interface for electrically coupling the IC carrier package circuitry to a printed circuit board. The connector interface is further characterized as having a graduated step surface contour with one or more electrical contacts disposed on at least two graduated step connector surfaces of the connector interface. The electronic assembly further includes a multilayer printed circuit board having a mounting site cavity for mounting the IC carrier package. The mounting site cavity includes having at least two seating surfaces offset in a graduated step manner for receivably seating the at least two graduated step connector surfaces of the IC carrier package connector interface.

摘要翻译： 本文公开了一种实现其的电子组件及其系统和方法。 电子组件包括具有包含在壳体单元内的电路的IC载体封装。 IC载体封装包括用于将IC载体封装电路电耦合到印刷电路板的连接器接口。 连接器接口的特征还在于具有刻度的台阶表面轮廓，其中一个或多个电触点设置在连接器接口的至少两个刻度的步骤连接器表面上。 电子组件还包括具有用于安装IC载体封装的安装位置腔的多层印刷电路板。 安装位置腔包括具有以刻度步长方式偏移的至少两个就座表面，用于可接收地安置IC载体封装连接器接口的至少两个刻度级连接器表面。

公开(公告)号：US20070073529A1

公开(公告)日：2007-03-29

申请号：US11239600

申请日：2005-09-29

申请人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

发明人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/86

摘要： An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer to simulate using one model that captures the anticipated extremes (best case behavior to worst case behavior) across a collection of devices from different vendors.

摘要翻译： 使用具有多个部分的复合行为信息的单一模型来模拟和测试电子系统的装置和方法。 单一模型允许设计人员使用一个模型来模拟来自不同供应商的一组设备的捕获预期极限（最佳情况行为到最坏情况行为）。

公开(公告)号：US20070236895A1

公开(公告)日：2007-10-11

申请号：US11393140

申请日：2006-03-30

申请人： Gerald Bartley ,  Richard Ericson ,  Mark Hoffmeyer ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

发明人： Gerald Bartley ,  Richard Ericson ,  Mark Hoffmeyer ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

IPC分类号： H05K1/14

CPC分类号： H05K1/167 ,  H05K1/116 ,  H05K3/027 ,  H05K3/429 ,  H05K2203/171

摘要： A via resistor structure and method are provided for implementing a resistor and for trimming a resistance value of the resistor. A resistive material selectively is deposited adjacent to a pad connecting to a via where a resistor is to be defined. A trimmed path is formed in the resistive material for selectively changing the resistance value of the resistor.

摘要翻译： 提供了一种通过电阻器结构和方法来实现电阻器并且用于微调电阻器的电阻值。 电阻材料选择性地沉积在连接到要限定电阻器的通孔的焊盘附近。 在电阻材料中形成修整路径，用于选择性地改变电阻器的电阻值。

公开(公告)号：US20050153584A1

公开(公告)日：2005-07-14

申请号：US10753521

申请日：2004-01-08

申请人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

发明人： Gerald Bartley ,  Richard Ericson ,  Wesley Martin ,  Benjamin Mashak ,  Trevor Timpane ,  Ay Vang

IPC分类号： H01R4/60 ,  H01R12/00 ,  H01R13/26 ,  H01R13/658

CPC分类号： H01R13/6477 ,  H01R13/26 ,  H01R2101/00

摘要： A high frequency connector utilizes flex strip signal/reference conductor pairs extending in channels formed in a dielectric connector body between terminations at connector ends. The flex strips are formed as signal and reference conductor traces separated by a flexible dielectric wherein the impedance can be influenced by the width of the signal and reference traces and the thickness and selected material of the dielectric separating the adjoining conductor traces. Design of the flex strip assemblies is used to vary the capacitance which enables the connector impedance to match the impedance of the circuits and/or cables connected to the connector and mitigate any discontinuities among the sequence of circuit paths. The close proximity of signal and reference traces within the pair and the separation of signal lines in the connector body reduces cross talk by minimizing mutual inductance between signal lines.