公开(公告)号：US5294568A

公开(公告)日：1994-03-15

申请号：US867299

申请日：1992-04-10

申请人： Michael A. McNeilly ,  Bruce E. Deal ,  Dah-Bin Kao ,  John de Larios

发明人： Michael A. McNeilly ,  Bruce E. Deal ,  Dah-Bin Kao ,  John de Larios

IPC分类号： C04B41/53 ,  H01L21/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L21/02046 ,  C04B41/5346 ,  H01L21/31116 ,  H01L21/67069 ,  Y10S148/017 ,  Y10S148/051 ,  Y10S438/906 ,  Y10S438/974

摘要： A method of selective etching of native oxide on a substrate is disclosed in which hydrogen halide vapor and water vapor are exposed to the substrate surface under appropriate conditions and long enough to remove native oxide but not long enough to remove any significant amount of other oxides. Treating conditions are maintained to prevent water vapor from condensing on the substrate until sufficient native oxide is etched so that substantially all the native oxide will be etched before appreciable other oxides are etched.

摘要翻译： 公开了一种在衬底上选择性蚀刻天然氧化物的方法，其中卤化氢蒸汽和水蒸汽在合适的条件下暴露于衬底表面，并足够长的时间以除去天然氧化物，但不足以除去任何显着量的其它氧化物。 保持处理条件以防止水蒸汽在基底上冷凝，直到蚀刻足够的自然氧化物，使得在可观的其它氧化物被蚀刻之前基本上所有的天然氧化物将被蚀刻。

公开(公告)号：US4442449A

公开(公告)日：1984-04-10

申请号：US243986

申请日：1981-03-16

申请人： William I. Lehrer ,  Bruce E. Deal

发明人： William I. Lehrer ,  Bruce E. Deal

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/43 ,  H01L29/163 ,  H01L29/54

CPC分类号： H01L23/53271 ,  H01L21/76886 ,  H01L2924/0002 ,  Y10S428/929 ,  Y10T428/12528 ,  Y10T428/12674

摘要： An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type commonly used in the semiconductor industry. The resulting alloy can be oxidized, selectively removed and doped with selected impurities to provide a conductive lead pattern of a desired shape on the surface of a wafer.

摘要翻译： 用于集成电路的互连结构包括锗 - 硅二元合金。 使用在半导体工业中通常使用的类型的化学气相沉积技术，这种合金由锗和硅的共沉积沉积在半导体晶片上。 所得合金可以被氧化，选择性地除去并掺杂选定的杂质，以在晶片的表面上提供所需形状的导电引线图形。

公开(公告)号：US4027380A

公开(公告)日：1977-06-07

申请号：US649957

申请日：1976-01-16

申请人： Bruce E. Deal ,  Daniel C. Hu

发明人： Bruce E. Deal ,  Daniel C. Hu

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/00 ,  B01J17/00

CPC分类号： H01L21/00 ,  H01L21/76218 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/00 ,  Y10S148/003 ,  Y10S148/04 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/118 ,  Y10S148/141

摘要： A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q.sub.ss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

摘要翻译： 在相同的半导体衬底中具有互补的p沟道和n沟道器件的互补绝缘栅场效应晶体管结构和用于制造该结构的工艺结合了活性器件区的氧化物隔离，p阱与相反类型杂质的反掺杂 以获得复合掺杂分布，在隔离氧化物中减少Qss，用氯物质掺杂栅极和场氧化物并掺杂多晶硅栅极。