公开(公告)号：US08803715B2

公开(公告)日：2014-08-12

申请号：US13365710

申请日：2012-02-03

申请人： Fang-Shi Jordan Lai ,  Yung-Fu Lin ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng

发明人： Fang-Shi Jordan Lai ,  Yung-Fu Lin ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng

IPC分类号： H03M1/10

CPC分类号： H03M1/1004 ,  H03M1/1057 ,  H03M1/74

摘要： Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.

摘要翻译： 公开了校准SDM（Σ-Δ调制器）的数模转换器（DAC）的机制。 除了DAC之外还有一个额外的DAC元件用于代替校准下的DAC元件。 在校准下将信号（例如，-1和+1的随机序列）注入DAC元件，并且获得估计的误差和补偿。

公开(公告)号：US08441384B2

公开(公告)日：2013-05-14

申请号：US13030862

申请日：2011-02-18

申请人： Fang-Shi Lai ,  Manoj M. Mhala ,  Yung-Fu Lin ,  Hsu-Feng Hsueh ,  Chin-Hao Chang ,  Cheng Yen Weng

发明人： Fang-Shi Lai ,  Manoj M. Mhala ,  Yung-Fu Lin ,  Hsu-Feng Hsueh ,  Chin-Hao Chang ,  Cheng Yen Weng

IPC分类号： H03M3/00

CPC分类号： H03K5/24 ,  H03M3/352 ,  H03M3/45 ,  H03M3/452

摘要： A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.

摘要翻译： 公开了一种开关电容器电路。 开关电容器电路包括具有第一和第二输入，第一和第二采样电容器以及第一和第二开关电路的比较器。 第一开关电路用输入信号对第一和第二采样电容器充电。 第二开关电路选择性地将第一采样电容器与参考电压耦合，并且将第二采样电容器和比较器的第一和第二输入端选择性地耦合到公共电压。 比较器执行输入信号与参考电压的比较，并输出信号。

公开(公告)号：US08279102B2

公开(公告)日：2012-10-02

申请号：US12898261

申请日：2010-10-05

申请人： Fang-Shi Jordan Lai ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin ,  Manoj M. Mhala ,  Tao Wen Chung ,  Chin-Hao Chang

发明人： Fang-Shi Jordan Lai ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin ,  Manoj M. Mhala ,  Tao Wen Chung ,  Chin-Hao Chang

IPC分类号： H03M1/38

CPC分类号： H03M1/1215 ,  H03M1/164 ,  H03M1/442

摘要： An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.

摘要翻译： 模数转换器（ADC）包括具有可变模拟输入电压的输入节点，第一和第二开关电容器电路，运算放大器和控制电路。 第一开关电容器电路具有第一和第二电容器并且耦合到输入节点，并且第二开关电容器电路具有第三和第四电容器并且耦合到输入节点。 运算放大器被配置为一次有条件地耦合到第一和第二开关电容器电路中的一个，并且被配置为通过输出节点有条件地向开关电容器电路提供反馈。 控制电路耦合到第一和第二开关电容器电路以用于与运算放大器的条件耦合。

公开(公告)号：US08223047B2

公开(公告)日：2012-07-17

申请号：US12844150

申请日：2010-07-27

申请人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

发明人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  H03M1/1004 ,  H03M1/365

摘要： An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual.

摘要翻译： 模数转换器（ADC）包括多个比较器，其中之一被称为辅助比较器（例如，比较器“Aux”）。 该比较器Aux在后台校准，而其他比较器的功能如常。 一旦被校准，比较器Aux将替换成为新的比较器Aux的第一比较器，并且替换第二比较器。 第二个比较器成为新的比较器Aux，被校准，并替换第三个比较器等，直到所有的比较器被校准。 实际上，在任何一个时间点，可以根据需要对比较器进行校准，而其他比较器因此ADC正常运行。

公开(公告)号：US20120133536A1

公开(公告)日：2012-05-31

申请号：US13365710

申请日：2012-02-03

申请人： Fang-Shi Jordan LAI ,  Yung-Fu LIN ,  Kuo-Ming WANG ,  Hsu-Feng HSUEH ,  Cheng Yen WENG

发明人： Fang-Shi Jordan LAI ,  Yung-Fu LIN ,  Kuo-Ming WANG ,  Hsu-Feng HSUEH ,  Cheng Yen WENG

IPC分类号： H03M1/10 ,  H03M3/02

CPC分类号： H03M1/1004 ,  H03M1/1057 ,  H03M1/74

摘要： Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.

摘要翻译： 公开了校准SDM（Σ-Δ调制器）的数模转换器（DAC）的机制。 除了DAC之外还有一个额外的DAC元件用于代替校准下的DAC元件。 在校准下将信号（例如，-1和+1的随机序列）注入DAC元件，并且获得估计的误差和补偿。

公开(公告)号：US20120081244A1

公开(公告)日：2012-04-05

申请号：US12898261

申请日：2010-10-05

申请人： Fang-Shi Jordan LAI ,  Hsu-Feng HSUEH ,  Cheng Yen WENG ,  Yung-Fu LIN ,  Manoj M. MHALA ,  Tao Wen CHUNG ,  Chin-Hao CHANG

发明人： Fang-Shi Jordan LAI ,  Hsu-Feng HSUEH ,  Cheng Yen WENG ,  Yung-Fu LIN ,  Manoj M. MHALA ,  Tao Wen CHUNG ,  Chin-Hao CHANG

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/1215 ,  H03M1/164 ,  H03M1/442

摘要： An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.

摘要翻译： 模数转换器（ADC）包括具有可变模拟输入电压的输入节点，第一和第二开关电容器电路，运算放大器和控制电路。 第一开关电容器电路具有第一和第二电容器并且耦合到输入节点，并且第二开关电容器电路具有第三和第四电容器并且耦合到输入节点。 运算放大器被配置为一次有条件地耦合到第一和第二开关电容器电路中的一个，并且被配置为通过输出节点有条件地向开关电容器电路提供反馈。 控制电路耦合到第一和第二开关电容器电路以用于与运算放大器的条件耦合。

公开(公告)号：US07893853B2

公开(公告)日：2011-02-22

申请号：US12347014

申请日：2008-12-31

申请人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

发明人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

IPC分类号： H03M1/10

CPC分类号： H03M1/1057

摘要： A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.

摘要翻译： 提供了一种校准数模转换器（DAC）的方法。 DAC包括最低有效位（LSB）块和与LSB块相邻的虚拟LSB块。 DAC具有最高有效位（MSB）块，其中包含MSB温度计宏。 该方法包括测量虚拟LSB块以获得虚拟LSB和; 并校准MSB块，使得每个MSB温度计宏提供与虚拟LSB总和大致相同的电流。

公开(公告)号：US20120212359A1

公开(公告)日：2012-08-23

申请号：US13029754

申请日：2011-02-17

申请人： Fang-Shi Jordan Lai ,  Chin-Hao Chang ,  Manoj M. Mhala ,  Hsu-Feng Hsueh ,  Yung-Fu Lin ,  Cheng Yen Weng

发明人： Fang-Shi Jordan Lai ,  Chin-Hao Chang ,  Manoj M. Mhala ,  Hsu-Feng Hsueh ,  Yung-Fu Lin ,  Cheng Yen Weng

IPC分类号： H03M1/10 ,  H03K5/22

CPC分类号： H03M1/1061 ,  H03M1/361

摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.

摘要翻译： 模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。 每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。 比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。 基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。 通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。

公开(公告)号：US08416105B2

公开(公告)日：2013-04-09

申请号：US13029754

申请日：2011-02-17

申请人： Fang-Shi Jordan Lai ,  Chin-Hao Chang ,  Manoj M. Mhala ,  Hsu-Feng Hsueh ,  Yung-Fu Lin ,  Cheng Yen Weng

发明人： Fang-Shi Jordan Lai ,  Chin-Hao Chang ,  Manoj M. Mhala ,  Hsu-Feng Hsueh ,  Yung-Fu Lin ,  Cheng Yen Weng

IPC分类号： H03M1/10

CPC分类号： H03M1/1061 ,  H03M1/361

摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.

摘要翻译： 模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。 每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。 比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。 基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。 通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。

公开(公告)号：US08279097B2

公开(公告)日：2012-10-02

申请号：US12775104

申请日：2010-05-06

申请人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

发明人： Fang-Shi Jordan Lai ,  Kuo-Ming Wang ,  Hsu-Feng Hsueh ,  Cheng Yen Weng ,  Yung-Fu Lin

IPC分类号： H03M1/10

CPC分类号： H03M1/1042 ,  H03M1/1004 ,  H03M1/168

摘要： A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.

摘要翻译： 一种操作模数转换器（ADC）的方法包括提供包括多个级的ADC，每个级分别包括运算放大器，以及分别包括第一输入端和第二输入端的第一电容器和第二电容器 。 第一电容器和第二电容器中的每一个包括连接到运算放大器的相同输入端的附加端。 该方法还包括执行多个信号转换。 每个信号转换在多级中的一个级的放大阶段中包括将第一电压施加到多级中的一级的第一输入端，从两个不同电压随机选择第二电压; 以及将所述第二电压施加到所述多个级中的所述一个级的所述第二输入端。