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公开(公告)号:US20130280900A1
公开(公告)日:2013-10-24
申请号:US13454337
申请日:2012-04-24
申请人: Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
发明人: Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
IPC分类号: H01L21/283
CPC分类号: H01L21/823842 , H01L29/66545
摘要: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
摘要翻译: 提供一种具有金属栅极的半导体器件的制造方法。 第一和第二栅极沟槽分别形成在第一和第二半导体器件中。 工作功能金属层形成在第一和第二栅极沟槽中。 在基板上形成屏蔽层。 执行第一去除步骤,使得剩余的屏蔽层位于第二栅极沟槽的底部并填充第一栅极沟槽。 执行第二去除步骤,使得剩余的屏蔽层位于第一栅极沟槽的底部,以在第一栅极沟槽的侧壁和第二栅极沟槽中露出功函数金属层。 除去未被剩余屏蔽层覆盖的功函数金属层,使剩余的功函数金属层仅在第一栅极沟槽的底部。 剩下的屏蔽层被去除。
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公开(公告)号:US08486842B2
公开(公告)日:2013-07-16
申请号:US12901453
申请日:2010-10-08
申请人: Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen
发明人: Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen
IPC分类号: H01L21/302
CPC分类号: H01L21/31144 , H01L27/0629 , H01L28/24
摘要: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.
摘要翻译: 描述了选择性地去除图案化的硬掩模的方法。 提供了其上具有图案化目标层的衬底,其中所述图案化目标层包括第一目标图案和至少一个第二目标图案,并且所述图案化硬掩模包括第一目标图案上的第一掩模图案和第二掩模图案 所述至少一个第二目标图案。 形成覆盖第一掩模图案的第一光致抗蚀剂层。 所述至少一个第二目标图案的侧壁被第二光致抗蚀剂层覆盖。 使用第一光致抗蚀剂层和第二光致抗蚀剂层作为掩模去除第二掩模图案。
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公开(公告)号:US20120214284A1
公开(公告)日:2012-08-23
申请号:US13461791
申请日:2012-05-02
IPC分类号: H01L21/8234
CPC分类号: H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译: 集成方法包括制造金属栅极晶体管和多晶硅电阻器结构。 光电晶体层由SAB光掩模限定,并覆盖多晶硅电阻器的高电阻结构的一部分。 当蚀刻晶体管的虚拟栅极时,高电阻结构的部分被图案化的光敏电阻层保护。 多晶硅电阻器与晶体管同时形成。 此外,多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。
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公开(公告)号:US20120070952A1
公开(公告)日:2012-03-22
申请号:US12883233
申请日:2010-09-16
申请人: Che-Hua HSU , Shao- Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
发明人: Che-Hua HSU , Shao- Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
IPC分类号: H01L21/336
CPC分类号: H01L29/66545 , H01L21/823456 , H01L21/823468 , H01L29/6656
摘要: A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
摘要翻译: 硬掩模的去除方法包括以下步骤。 提供基板。 在衬底上形成至少两个MOSFET。 在衬底中形成隔离结构,并且位于至少两个MOSFET之间。 MOSEFT中的每一个在栅极上包括栅极绝缘层,栅极,间隔物和硬掩模。 在隔离结构上形成保护结构,从保护结构露出硬掩模。 暴露的硬掩模被移除以露出门。
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公开(公告)号:US20110012205A1
公开(公告)日:2011-01-20
申请号:US12889410
申请日:2010-09-24
申请人: Chien-Ting Lin , Che-Hua Hsu , Li-Wei Cheng
发明人: Chien-Ting Lin , Che-Hua Hsu , Li-Wei Cheng
IPC分类号: H01L29/49
CPC分类号: H01L21/28123 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要: A metal gate structure is disclosed. The metal gate structure includes: a semiconductor substrate having an active region and an isolation region; an isolation structure disposed in the isolation region; a first gate structure disposed on the active region; and a second gate structure disposed on the isolation structure, wherein the height of the second gate structure is different from the height of the first gate structure.
摘要翻译: 公开了一种金属栅极结构。 金属栅极结构包括:具有有源区和隔离区的半导体衬底; 设置在所述隔离区域中的隔离结构; 设置在所述有源区上的第一栅极结构; 以及设置在所述隔离结构上的第二栅极结构,其中所述第二栅极结构的高度不同于所述第一栅极结构的高度。
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公开(公告)号:US20100327378A1
公开(公告)日:2010-12-30
申请号:US12493074
申请日:2009-06-26
CPC分类号: H01L21/28088 , H01L27/0629 , H01L28/20 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
摘要翻译: 提供半导体结构及其形成方法。 半导体结构包括衬底,电阻器和金属栅极结构。 衬底具有第一区域和第二区域。 电阻器设置在第一区域中,其中电阻器不包括任何金属层。 金属栅极结构设置在第二区域中。
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公开(公告)号:US20100317182A1
公开(公告)日:2010-12-16
申请号:US12862799
申请日:2010-08-25
申请人: Tian-Fu Chiang , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Yi-Wen Chen , Chien-Ting Lin , Guang-Hwa Ma
发明人: Tian-Fu Chiang , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Yi-Wen Chen , Chien-Ting Lin , Guang-Hwa Ma
IPC分类号: H01L21/8234
CPC分类号: H01L29/517 , H01L21/823842 , H01L21/823871 , H01L27/11 , H01L27/1104 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.
摘要翻译: 提供一种形成半导体元件结构的方法。 首先,提供包括第一MOS和第二MOS的基板。 第一MOS的栅电极连接到第二MOS的栅电极,其中第一MOS包括第一高K材料和用于第一栅极的第一金属,第二MOS包括第二高K 材料和用于第二栅极的第二金属。 然后,第一栅极和第二栅极被部分地去除以形成连接凹部。 之后,用导电材料填充连接凹部,以形成用于电连接第一金属和第二金属的桥接通道。
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公开(公告)号:US07816243B2
公开(公告)日:2010-10-19
申请号:US12372908
申请日:2009-02-18
申请人: Chun-Fei Chuang , Chien-Ting Lin , Che-Hua Hsu , Shao-Hua Hsu , Cheng-I Lin
发明人: Chun-Fei Chuang , Chien-Ting Lin , Che-Hua Hsu , Shao-Hua Hsu , Cheng-I Lin
IPC分类号: H01L21/4763
CPC分类号: H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要: A semiconductor device and a method of fabricating the same are described. A substrate having a PMOS area and an NMOS area is provided. A high-k layer is formed on the substrate. A first cap layer is formed on the high-k layer in the PMOS area, and a second cap layer is formed on the high-k layer in the NMOS area, wherein the first cap layer is different from the second cap layer. A metal layer and a polysilicon layer are sequentially formed on the first and second cap layers. The polysilicon layer, the metal layer, the first cap layer, the second cap layer and the high-k layer are patterned to form first and second gate structures respectively in the PMOS and NMOS areas. First source/drain regions are formed in the substrate beside the first gate structure. Second source/drain regions are formed in the substrate beside the second gate structure.
摘要翻译: 对半导体器件及其制造方法进行说明。 提供具有PMOS区域和NMOS区域的衬底。 在基板上形成高k层。 在PMOS区域的高k层上形成第一覆盖层,在NMOS区域的高k层上形成第二覆盖层,其中第一覆盖层与第二覆盖层不同。 在第一和第二盖层上依次形成金属层和多晶硅层。 图案化多晶硅层,金属层,第一覆盖层,第二覆盖层和高k层,以在PMOS和NMOS区域中分别形成第一和第二栅极结构。 在第一栅极结构旁边的基板中形成第一源极/漏极区域。 第二源极/漏极区域形成在第二栅极结构旁边的衬底中。
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公开(公告)号:US09490342B2
公开(公告)日:2016-11-08
申请号:US13161591
申请日:2011-06-16
申请人: Chien-Ming Lai , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
发明人: Chien-Ming Lai , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
IPC分类号: H01L21/3205 , H01L29/66 , H01L21/8238 , H01L21/28 , H01L21/3213 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号: H01L29/6659 , H01L21/28088 , H01L21/32134 , H01L21/823842 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
摘要翻译: 一种制造半导体器件的方法包括以下步骤。 首先,提供具有伪栅极电极层的虚拟栅极结构。 然后,去除虚拟栅极电极层,以在虚拟栅极结构中形成开口,从而暴露在伪栅极电极层下面的下面的层。 然后,进行氢氧化铵处理处理以处理伪栅极结构。 之后,将金属材料填充到开口中。
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公开(公告)号:US08232152B2
公开(公告)日:2012-07-31
申请号:US12883233
申请日:2010-09-16
申请人: Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
发明人: Che-Hua Hsu , Shao-Hua Hsu , Zhi-Cheng Lee , Cheng-Guo Chen , Shin-Chi Chen , Hung-Ling Shih , Hung-Yi Wu , Heng-Ching Huang
IPC分类号: H01L21/336
CPC分类号: H01L29/66545 , H01L21/823456 , H01L21/823468 , H01L29/6656
摘要: A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
摘要翻译: 硬掩模的去除方法包括以下步骤。 提供基板。 在衬底上形成至少两个MOSFET。 在衬底中形成隔离结构,并且位于至少两个MOSFET之间。 MOSEFT中的每一个在栅极上包括栅极绝缘层,栅极,间隔物和硬掩模。 在隔离结构上形成保护结构,从保护结构露出硬掩模。 暴露的硬掩模被移除以露出门。
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