公开(公告)号：US4637039A

公开(公告)日：1987-01-13

申请号：US698990

申请日：1985-02-07

申请人： Cornelis M. Huizer

发明人： Cornelis M. Huizer

IPC分类号： H03K23/00 ,  H03K3/356 ,  H03K23/60

CPC分类号： H03K3/356034

摘要： In order to reduce the likelihood of incorrect states being transferred from one cross-coupled transistor pair to the next in a frequency divider which comprises at least two such pairs (6a, 7a and 8a, 9a) which are energized alternately by means of a switchable current source arrangement (5) and which are inter-coupled to form a cyclic arrangement by means of data transfer transistors (6b, 7b, 8b and 9b) energized from the same outputs (22, 23) of the current source arrangement, the transistors employed are of the insulated gate field effect type. The channel width-to-length ratios of the pair transistors (6a, 7a, 8a, 9a) may be chosen to be different from the corresponding ratios for the data transfer transistors (6b, 7b, 8b, 9b) in order to improve either the high-frequency or the low frequency performance in accordance with the sign of such difference.

摘要翻译： 为了减少错误状态从包括至少两个这样的对（6a，7a和8a，9a）的分频器中的一个交叉耦合晶体管对传输到下一个的可能性，它们通过可切换的 电流源装置（5），并且它们通过从电流源装置的相同输出端（22,23）供电的数据传输晶体管（6b，7b，8b和9b）互相耦合以形成循环布置，晶体管 采用绝缘栅场效应型。 可以选择对晶体管（6a，7a，8a，9a）的沟道宽长比来与数据传输晶体管（6b，7b，8b，9b）的相应比率不同，以便改善 高频或低频性能符合这样的差异。

公开(公告)号：US06751802B1

公开(公告)日：2004-06-15

申请号：US08683994

申请日：1996-07-19

申请人： Cornelis M. Huizer ,  Lucas M. W. M. Karel ,  Frank Bosveld ,  Pieter Jan De Visser

发明人： Cornelis M. Huizer ,  Lucas M. W. M. Karel ,  Frank Bosveld ,  Pieter Jan De Visser

IPC分类号： H04N7173

CPC分类号： H04N7/17318 ,  G06T9/007 ,  H04N21/2387 ,  H04N21/47202 ,  H04N21/8455

摘要： The invention relates to the transmission of MPEG encoded television signals from a Video-On-Demand server (1) to a receiver (2) via a network (3). Non-linear playback functions such as ‘pause’ and ‘resume’ require a very accurate control of the bit stream, taking account of typical network aspects such as network latency and remultiplexing. In order to allow the receiver to flawlessly resume signal reproduction after a pause, position labels (p; 5,6; 7a,7b,8a,8b) are inserted into the bit stream at positions where the server can resume transmission of the signal after an interruption. Upon a pause request, the decoder initially continues the reproduction until such a position label is detected. The subsequent bits delivered by the network are ignored, i.e. they are thrown away. Upon a request to resume reproduction, the receiver requests the server to retransmit the signal starting at the detected position.

摘要翻译： 本发明涉及通过网络（3）将MPEG编码电视信号从视频点播服务器（1）发送到接收机（2）。 诸如“暂停”和“恢复”之类的非线性重放功能需要对比特流进行非常精确的控制，考虑到典型的网络方面，如网络延迟和再复用。 为了允许接收机在暂停之后完美恢复信号再现，在服务器可以在服务器可以恢复发送信号之后的位置处将位置标签（p; 5,6; 7a，7b，8a，8b）插入位流中 中断 在暂停请求时，解码器最初继续再现，直到检测到这样的位置标签。 由网络传递的随后的比特被忽略，即被丢弃。 在请求恢复重放时，接收机请求服务器重传从检测位置开始的信号。

公开(公告)号：US5875303A

公开(公告)日：1999-02-23

申请号：US540514

申请日：1995-10-10

申请人： Cornelis M. Huizer ,  Peter B. Kaars ,  Balthasar A.G. Van Luijt ,  Frank Bosveld

发明人： Cornelis M. Huizer ,  Peter B. Kaars ,  Balthasar A.G. Van Luijt ,  Frank Bosveld

IPC分类号： H04N5/92 ,  G11B27/10 ,  G11B27/30 ,  H04N7/10 ,  H04N7/173 ,  H04N7/26 ,  H04N7/50 ,  H04N1/32

CPC分类号： H04N21/434 ,  G11B27/10 ,  G11B27/105 ,  G11B27/3063 ,  H04N19/61 ,  H04N21/236 ,  H04N7/17336 ,  G11B2220/2545

摘要： Disclosed are a method and arrangement for accessing interactive audiovisual programs stored on a remote server (1) by a multimedia station (2). The audiovisual program is stored in the same format as it is stored on a CDi disc, i.e. in the form of sectors. Although based on the same data compression technology, the CDi video coding standard does not comply with the MPEG coding specification. Moreover, MPEG does not cover the handling of specific CDi features. In order to allow conventional CDi decoders to access remotely stored CDi applications via interactive networks (3,4), the interactive audiovisual program is transmitted as a private MPEG2 data stream, using the concept of MPEG's transport stream. The multimedia station comprises a network interface (7) having a circuit (72) which assembles the transport packets and applies the signal sectorwise to a "stripped" CDi player (5,6).

摘要翻译： 公开了一种用于访问由多媒体站（2）存储在远程服务器（1）上的交互式视听节目的方法和装置。 视听节目以与存储在CDi盘上相同的格式存储，即以扇区的形式存储。 虽然基于相同的数据压缩技术，但CDi视频编码标准不符合MPEG编码规范。 此外，MPEG不包括特定CDi功能的处理。 为了允许传统的CDi解码器通过交互网络（3,4）访问远程存储的CDi应用，使用MPEG的传输流的概念将交互式视听节目作为专用MPEG2数据流传输。 多媒体站包括网络接口（7），该网络接口（7）具有电路（72），该电路组装传输分组并将信号扇区地应用于“剥离”的CDi播放器（5,6）。

公开(公告)号：US4691127A

公开(公告)日：1987-09-01

申请号：US801189

申请日：1985-11-25

申请人： Cornelis M. Huizer

发明人： Cornelis M. Huizer

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K17/14 ,  H03K19/003 ,  H03K1/02 ,  H03K17/30

CPC分类号： H03K19/00369 ,  H03K17/14 ,  H03K5/02

摘要： In an adaptive electronic buffer system in which a set circuit generates logic set signals for the buffer circuits, parallel sub-buffers are switched on or off by the set signals, so that the specified charging and discharging times of the output can be achieved. This setting compensates for the manufacturing process variations and operating conditions (temperature, supply voltage) of the buffer circuits. The spread in the output conductance is reduced, thus reducing the risk of fast current variations, inductive voltage peaks and the associated loss of data.

摘要翻译： 在设置电路产生用于缓冲电路的逻辑设置信号的自适应电子缓冲器系统中，通过设定信号将并行子缓冲器接通或断开，从而可以实现输出的规定的充电和放电时间。 该设置补偿了缓冲电路的制造工艺变化和工作条件（温度，电源电压）。 输出电导的扩展减小，从而降低快速电流变化，感应电压峰值以及相关的数据丢失的风险。

公开(公告)号：US5950005A

公开(公告)日：1999-09-07

申请号：US800448

申请日：1997-02-18

申请人： Gerard J. Elbers ,  Cornelis M. Huizer

发明人： Gerard J. Elbers ,  Cornelis M. Huizer

IPC分类号： G06F11/34 ,  G06F3/14 ,  G06F3/16 ,  G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F17/00 ,  G06F17/30 ,  G06F9/455

CPC分类号： G06F17/30017

摘要： A multimedia application title is stored for execution on different platforms. Associated to the title is an occurrence table that lists the number of occurrences of each of at least a substantial fraction of all operations in the application, and also an execution profile table that lists the relative execution occurrence frequencies of each of at least a substantial fraction of all operations in the application. When loading the application title, its occurrence and execution profile tables are accessed. Through OP2INS and MOPS2MIPS conversion data for each operation, memory and processing requirements for executing the title are evaluated and an evaluation result signalled to a user.

摘要翻译： 存储多媒体应用程序标题以在不同的平台上执行。 与标题相关联的是出现表，其列出应用程序中所有操作的至少大部分的至少大部分的出现次数，以及执行简档表，其列出至少相当大部分中的每一个的相对执行发生频率 在应用程序中的所有操作。 加载应用程序标题时，会访问其出现和执行概要文件表。 通过每个操作的OP2INS和MOPS2MIPS转换数据，评估用于执行标题的存储器和处理要求，并向用户发出评估结果。

公开(公告)号：US5612981A

公开(公告)日：1997-03-18

申请号：US196918

申请日：1994-02-15

申请人： Cornelis M. Huizer

发明人： Cornelis M. Huizer

IPC分类号： H04N7/26 ,  H03L1/00 ,  H03L7/06 ,  H03L7/10 ,  H03L7/18 ,  H04L7/033 ,  H04N5/12 ,  H04N21/43 ,  H03D3/24

CPC分类号： H04N5/126 ,  H03L1/00 ,  H03L7/10 ,  H03L7/18 ,  H04N21/4305

摘要： Apparatus and methods for improving timing recovery of a system clock by causing its frequency to be within a specified tolerance range during a timing recovery acquisition period for the system clock. The apparatus includes a voltage controlled oscillator for producing the system clock and a non-volatile memory containing an offset value. The non-volatile memory provides an offset value (representing an offset voltage value) which assures that the voltage controlled oscillator receives a voltage value which causes the frequency of the system clock to be within a specified tolerance range. The apparatus may also include a write control unit for determining and updating the offset value for a next timing recovery acquisition period. The methods include steps for performing these operations.

摘要翻译： 用于通过在系统时钟的定时恢复获取周期期间使其频率在指定的公差范围内来改善系统时钟的定时恢复的装置和方法。 该装置包括用于产生系统时钟的压控振荡器和包含偏移值的非易失性存储器。 非易失性存储器提供偏移值（表示偏移电压值），其确保压控振荡器接收使得系统时钟的频率在特定公差范围内的电压值。 该装置还可以包括写入控制单元，用于确定和更新下一个定时恢复获取周期的偏移值。 这些方法包括执行这些操作的步骤。

公开(公告)号：US5264738A

公开(公告)日：1993-11-23

申请号：US891314

申请日：1992-05-29

申请人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. Van Den Elshout ,  Cornelis M. Huizer

发明人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. Van Den Elshout ,  Cornelis M. Huizer

IPC分类号： H03K3/037 ,  H03K3/3562 ,  H03K5/13 ,  H03K3/26 ,  H03K19/096

CPC分类号： H03K3/0375 ,  H03K3/0372 ,  H03K3/35625

摘要： The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

公开(公告)号：US5109488A

公开(公告)日：1992-04-28

申请号：US316720

申请日：1989-02-28

申请人： Hendrik Dijkstra ,  Cornelis M. Huizer ,  Robert J. Sluijter

发明人： Hendrik Dijkstra ,  Cornelis M. Huizer ,  Robert J. Sluijter

IPC分类号： G06F5/06 ,  G06F7/78 ,  G06F12/02 ,  G11C19/00

CPC分类号： G06F7/785

摘要： A data processing system buffers sequential data for the duration of cyclically recurrent delay times. Memory location allocation is performed in such a way, that the memory is used efficiently without data-shifting after a read-out, and that the address generator is fairly simple.

公开(公告)号：US5103311A

公开(公告)日：1992-04-07

申请号：US593366

申请日：1990-10-01

申请人： Robert J. Sluijter ,  Cornelis M. Huizer ,  Hendrik Dijkstra ,  Gerrit A. Slavenburg

发明人： Robert J. Sluijter ,  Cornelis M. Huizer ,  Hendrik Dijkstra ,  Gerrit A. Slavenburg

IPC分类号： G06F3/14 ,  G06F9/30 ,  G06F9/38 ,  G06F15/16 ,  G06T1/20

CPC分类号： G06T1/20 ,  G06F9/3885

摘要： The invention describes a processor system suitable for processing video signal samples on a real-time basis. Signals are derived from the samples for driving an imaging unit. For this purpose, one or more processor modules are provided with processor elements, operating in parallel in time, which are connected to a crossbar switch. A module contains at least one arithmetic/logic processor element and at least one memory processor element. Moreover, there is a clock device, the frequency of which bears a fixed relationship to the frequency with which the video signal samples are obtained.

摘要翻译： 本发明描述了适用于实时地处理视频信号样本的处理器系统。 来自用于驱动成像单元的样本的信号。 为此，一个或多个处理器模块设置有与时间并行操作的处理器元件，其连接到交叉开关。 模块包含至少一个算术/逻辑处理器元件和至少一个存储器处理器元件。 此外，还有一个时钟装置，其频率与获得视频信号样本的频率具有固定的关系。

公开(公告)号：US5873022A

公开(公告)日：1999-02-16

申请号：US683993

申请日：1996-07-19

申请人： Cornelis M. Huizer ,  Lucas M.W.M. Karel ,  Frank Bosveld ,  Pieter J. De Visser

发明人： Cornelis M. Huizer ,  Lucas M.W.M. Karel ,  Frank Bosveld ,  Pieter J. De Visser

IPC分类号： H04N7/26 ,  G06T9/00 ,  H04N7/173 ,  H04N21/2387 ,  H04N21/472 ,  H04N21/845

CPC分类号： H04N7/17318 ,  G06T9/007 ,  H04N21/2387 ,  H04N21/47202 ,  H04N21/8455

摘要： The invention relates to the reception of MPEG encoded television signals from a Video-On-Demand server (1) via a network (3). Non-linear playback functions such as `pause` and `resume` require a very accurate control of the bit stream, taking account of typical network aspects such as network latency. The receiver (2) comprises a latency buffer (24) for storing the signal delivered while the reproduction is stalled. The pause and resume commands from the user are not forwarded to the server until the latency buffer reaches a predetermined fullness. This allows the receiver to resume flawlessly signal reproduction after a pause.

摘要翻译： 本发明涉及经由网络（3）从视频点播服务器（1）接收MPEG编码的电视信号。 诸如“暂停”和“恢复”之类的非线性重放功能需要对比特流进行非常精确的控制，考虑到典型的网络方面，如网络延迟。 接收器（2）包括用于存储在再现停止时传递的信号的等待时间缓冲器（24）。 来自用户的暂停和恢复命令不会转发到服务器，直到延迟缓冲区达到预定的丰满度。 这允许接收机在暂停之后恢复完美的信号再现。