公开(公告)号：US4700086A

公开(公告)日：1987-10-13

申请号：US726211

申请日：1985-04-23

申请人： Daniel T. Ling ,  Vojin G. Oklobdzija ,  Norman Raver

发明人： Daniel T. Ling ,  Vojin G. Oklobdzija ,  Norman Raver

IPC分类号： H03K19/096 ,  H03K17/687 ,  H03K19/173 ,  H03K19/003

CPC分类号： H03K19/1738

摘要： A precharge circuit for a cascode voltage switch in which at the beginning of the precharge phase the output state is memorized and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in their memorized states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

摘要翻译： 一种用于共源共栅电压开关的预充电电路，其中在预充电阶段开始时，存储输出状态并且输出与预充电点隔离。 放电路径的正端和负端均在保持在其存储状态的所有路径中的开关的栅极预充电。 在预充电结束时，输出将重新连接到正常的预充电点，使其变低。 然后将正，负预充电点重新连接起来进行评估。

公开(公告)号：US4714994A

公开(公告)日：1987-12-22

申请号：US728724

申请日：1985-04-30

申请人： Vojin G. Oklobdzija ,  Daniel T. Ling

发明人： Vojin G. Oklobdzija ,  Daniel T. Ling

IPC分类号： G06F9/38

CPC分类号： G06F9/381 ,  G06F9/3802

摘要： An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder ( 221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).

摘要翻译： 为指令预取缓冲器阵列（10）提供指令预取缓冲器控制（20），该指令预取缓冲器阵列（10）存储已经执行的多个指令的代码以及尚待执行的多个指令的代码。 指令预取缓冲器控制包括用于存储指令提取指针的寄存器（201），该指针作为写入指针提供给缓冲器阵列（10），该指针指向阵列中要写入新单词的位置， 主记忆 第二寄存器（205）存储作为读指针提供给缓冲器阵列（10）的指令执行指针。 第一加法器（203）递增第一寄存器以递增用于顺序指令的指令获取指针，并计算用于转移指令的新指令取指针。 第二加法器（215）递增第二寄存器以递增用于顺序指令的指令执行指针，并计算分支指令的新指令执行指针。 根据指令的长度，第二个寄存器的递增是可变的。 第三加法器（221）响应于第一加法器的输出和分支目标地址来计算目标指令是否包含在数组（10）中，并且如果是，则使得由第二加法器计算的新指令执行指针 加法器（215）被加载到第二寄存器（205）中。

公开(公告)号：US06553541B1

公开(公告)日：2003-04-22

申请号：US09544241

申请日：2000-04-05

申请人： Borivoje Nikolic ,  Leo Fu ,  Michael Leung ,  Vojin G. Oklobdzija ,  Richard Yamasaki

发明人： Borivoje Nikolic ,  Leo Fu ,  Michael Leung ,  Vojin G. Oklobdzija ,  Richard Yamasaki

IPC分类号： H03M1341

CPC分类号： G11B20/10064 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/10287 ,  G11B20/10296 ,  G11B20/1426 ,  G11B20/18 ,  H03M13/25 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6343 ,  H03M13/6502

摘要： Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The method is applied to the design of the E2PR4 channel with 8/9 rate sliding block trellis code. Coding, by itself eliminates two states by coding constraints, and the disclosed method reduces the number of required ACS units from 14 to 11, while reducing their complexity as well. For the implementation of E2PR4 detection, 4 4-way, 3 3-way, 3 2-way and one 1-way ACSs are needed. System simulations show no BER performance drop at common SNRs when compared with a full 16-state E2PR4 implementation in magnetic disk drives.

摘要翻译： 公开了维特比型序列检测器的复杂性的降低。 这是基于在网格中消除较少可能采取的分支。 该方法应用于具有8/9速率滑块网格码的E2PR4通道的设计。 编码本身通过编码约束消除了两个状态，并且所公开的方法将所需ACS单元的数量从14减少到11，同时降低了它们的复杂性。 为实现E2PR4检测，需要4路4路，3路，3路，1路ACS。 当与磁盘驱动器中的完全16状态E2PR4实现相比时，系统仿真显示在常见SNR下的BER性能下降。

公开(公告)号：US07509486B1

公开(公告)日：2009-03-24

申请号：US09611809

申请日：2000-07-07

申请人： David K. Chin ,  Vojin G. Oklobdzija ,  Aamir Farooqui

发明人： David K. Chin ,  Vojin G. Oklobdzija ,  Aamir Farooqui

IPC分类号： H04L29/00 ,  H04L9/00

CPC分类号： H04L63/0485 ,  G06F7/728 ,  G06F21/72 ,  H04L63/166

摘要： Methods and apparatus for an encryption processor for performing accelerated computations to establish secure network sessions. The encryption processor includes an execution unit and a decode unit. The execution unit is configured to execute Montgomery operations and including at least one adder and at least two multipliers. The decode unit is configured to determine if a square operation or a product operation needs to be performed and to issue the appropriate instructions so that certain multiply and/or addition operations are performed in parallel in the execution unit while performing either the Montgomery square or Montgomery product operation.

摘要翻译： 用于执行加速计算以建立安全网络会话的加密处理器的方法和装置。 加密处理器包括执行单元和解码单元。 执行单元被配置为执行蒙哥马利操作并且包括至少一个加法器和至少两个乘法器。 解码单元被配置为确定是否需要执行平方操作或产品操作，并且发出适当的指令，使得在执行单元中执行某些乘法和/或附加操作，同时执行蒙哥马利广场或蒙哥马利 产品操作。

公开(公告)号：US6128641A

公开(公告)日：2000-10-03

申请号：US928252

申请日：1997-09-12

申请人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Vojin G. Oklobdzija ,  Eric Chesters

发明人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Vojin G. Oklobdzija ,  Eric Chesters

IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/30054 ,  G06F9/462

摘要： The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.

摘要翻译： 本发明涉及一种在具有多个通用寄存器和上下文切换寄存器的寄存器文件的数据处理单元中的从第一任务到第二任务的上下文切换的方法，包括先前的上下文保存区域的存储器和 未使用的上下文保存区域。 存储器与寄存器文件和具有程序计数器寄存器的指令控制单元和与存储器和寄存器文件耦合的程序状态字寄存器耦合。 该方法包括以下步骤：从所述未使用的保存区域获取新的保存区域，将第一任务的上下文存储在所述新区域中，将新区域与所述先前的上下文保存区域相链接。

公开(公告)号：US06353843B1

公开(公告)日：2002-03-05

申请号：US09415485

申请日：1999-10-08

申请人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir A. Farooqui

发明人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir A. Farooqui

IPC分类号： G06F752

CPC分类号： G06F7/5324 ,  G06F7/49994 ,  G06F7/5338 ,  G06F2207/382

摘要： A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32×32 bit multiplication, two 16×16 bit multiplications (simultaneously) or four 8×8 bit multiplications (simultaneously) depending on input partitioning signals. The time required to perform either the 32×32 bit or the 16×16 bit or the 8×8 bit multiplications is constant. Therefore, multiplication results are available with a constant latency regardless of operand bit-size. In one embodiment, the latency is two clock cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The input operands can be signed or unsigned. The hardware is partitioned without any significant increase in the delay or area and the multiplier can provide six different modes of operation. In one embodiment, Booth encoding is used for the generation of 17 partial products which are compressed using a compression tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and a carry vector. These values are then added, in the second pipestage, using a carry propagate adder circuit to provide a single 64-bit result. In the case of 16×16 bit multiplication, the 64-bit result contains two 32-bit results. In the case of 8×8 bit multiplication, the 64-bit result contains four 16-bit results. Due to its high operating speed, the multiplier circuit is advantageous for use in multi-media applications, such as audio/visual rendering and playback.

摘要翻译： 分频乘法电路，专为高速运行而设计。 根据输入的分频信号，本发明的乘法器可以执行一个32×32位乘法，两次16×16位乘法（同时）或四个8×8位乘法（同时）。 执行32x32位或16x16位或8x8位乘法所需的时间是常数。 因此，无论操作数位大小如何，乘法结果都可以使用恒定的延迟。 在一个实施例中，等待时间是两个时钟周期，但乘法器电路由于流水线而具有一个时钟周期的吞吐量。 输入操作数可以是有符号的或无符号的。 硬件被分配，而延迟或区域没有任何显着增加，乘法器可以提供六种不同的操作模式。 在一个实施例中，布斯编码用于生成使用压缩树压缩为两个64位值的17个部分乘积。 这在第一流水线阶段执行以产生和和进位向量。 然后，在第二个管道中，使用进位传播加法器电路来添加这些值，以提供单个64位结果。 在16×16位乘法的情况下，64位结果包含两个32位结果。 在8×8位乘法的情况下，64位结果包含四个16位结果。 由于其高的操作速度，乘法器电路有利于在多媒体应用中使用，例如音频/视觉呈现和回放。

公开(公告)号：US06301599B1

公开(公告)日：2001-10-09

申请号：US09280176

申请日：1999-03-29

申请人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir Alam Farooqui

发明人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir Alam Farooqui

IPC分类号： G06F752

CPC分类号： G06F7/5338

摘要： An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two. The Booth encoder/selector is used in a multiplier circuit to minimize the number of partial products. An adder is then used to sum all of the partial products to arrive at the final answer. In the present invention, the critical path has been optimized such that the overall speed of the multiplier is greatly improved.

摘要翻译： 具有优化的关键路径的改进的布斯编码器/选择器电路。 布斯编码器具有耦合到多个输入乘法器位的多个反相器。 然后将反相/非反相乘法器位作为输入馈送到NAND门以及一系列通路。 然后将通过栅极的输出作为输入馈送到其他NAND门。 来自NAND门的输出用作控制Booth选择器的控制信号。 展位选择器由逆变​​器和通过门组成。 乘数位被输入到通过门。 由布斯编码器产生的控制信号选择性地耦合到反相器并传递门，使得它们控制多个被乘数位中的哪一个被选择用于输出。 基本上，展位选择器用作多路复用器，其中输出以下之一：被乘数位乘以零乘以1，乘以负1乘以2乘以乘以2。 Booth编码器/选择器用于乘法器电路中以最小化部分乘积的数量。 然后使用加法器来求出所有部分乘积以得出最终答案。 在本发明中，关键路径已被优化，使得乘法器的总体速度大大提高。

公开(公告)号：US06232810B1

公开(公告)日：2001-05-15

申请号：US09208618

申请日：1998-12-08

申请人： Vojin G. Oklobdzija ,  Vladimir Stojanovic

发明人： Vojin G. Oklobdzija ,  Vladimir Stojanovic

IPC分类号： H03K312

CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K3/356139

摘要： An improved SR latch has a two stages. A generation block generates Q and {overscore (Q)} signals from a set signal and a reset signal. The generation block also has an inactive state. A storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals at the voltage level that was output by the generation block prior to when the generation block blocks becomes inactive. In another embodiment, an improved D flip-flop has a sensing block with the improved SR latch of the present invention.

摘要翻译： 改进的SR锁存器有两个阶段。 生成块从设置信号和复位信号产生Q和{overscore（Q）}信号。 生成块也具有非活动状态。 存储块接收Q和{overscore（Q）}信号，并且在生成块块变为不活动之前将Q信号和{overscore（Q）}信号维持在由生成块输出的电压电平。 在另一个实施例中，改进的D触发器具有具有本发明的改进的SR锁存器的感测块。

公开(公告)号：US4992938A

公开(公告)日：1991-02-12

申请号：US469813

申请日：1990-04-23

申请人： John Cocke ,  Gregory F. Grohoski ,  Vojin G. Oklobdzija

发明人： John Cocke ,  Gregory F. Grohoski ,  Vojin G. Oklobdzija

IPC分类号： G06F9/38

CPC分类号： G06F9/3877 ,  G06F9/3836 ,  G06F9/384

摘要： A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

摘要翻译： 一种浮点指令控制机制，它与算术指令并行处理负载和存储。 这是由寄存器重命名引起的，这会删除指令控制机制中的输出依赖关系，允许将同一个寄存器进行别名的计算并行进行。

公开(公告)号：US4847759A

公开(公告)日：1989-07-11

申请号：US237615

申请日：1987-08-04

申请人： Vojin G. Oklobdzija

发明人： Vojin G. Oklobdzija

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/3802

摘要： A register selection mechanism for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is responsive to a read pointer (15) for controlling access to odd and oven addresses in the array. Additional logic may be provided to provide an indication that the instruction prefetch buffer is empty.

摘要翻译： 用于指令预取缓冲器的寄存器选择机制，其允许在指令边界上访问具有不同长度的指令。 指令预取缓冲器包括单端口写入双端口读取阵列（10）。 地址生成和控制逻辑（16）响应于读指针（15）来控制对阵列中的奇数和加热炉地址的访问。 可以提供附加逻辑以提供指令预取缓冲器为空的指示。