公开(公告)号：US07203827B2

公开(公告)日：2007-04-10

申请号：US11069771

申请日：2005-03-01

Applicant: David A. Kruckemyer ,  Daniel C. Murray

Inventor： David A. Kruckemyer ,  Daniel C. Murray

IPC: G06F9/32

CPC classification number: G06F9/324 ,  G06F9/30054 ,  G06F9/3806

Abstract: A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

Abstract translation: 提供链路地址/顺序地址生成电路用于生成链路/顺序地址。 该电路接收至少两个地址的最高有效位：包括分支指令的第一组字节的第一地址和与第一组相邻的第二组字节的第二地址。 分支PC的最低有效位（不包括在由电路接收的地址的最高有效位中的位）被用于生成链路/顺序地址的最低有效位，并且选择第一地址和 第二个地址提供最重要的位。

公开(公告)号：US06976152B2

公开(公告)日：2005-12-13

申请号：US10066941

申请日：2002-02-04

Applicant: Tse-Yu Yeh ,  David A. Kruckemyer ,  Randel P. Blake-Campos ,  Robert Rogenmoser ,  Robert Stepanian

Inventor： Tse-Yu Yeh ,  David A. Kruckemyer ,  Randel P. Blake-Campos ,  Robert Rogenmoser ,  Robert Stepanian

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863

Abstract: An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.

Abstract translation: 用于处理器的装置包括第一记分板，第二记分板和耦合到第一记分板和第二记分板的控制电路。 控制电路被配置为响应于将第一指令发布到第一管道中而更新第一记分板以指示针对第一指令的第一目的地寄存器的等待写入。 控制电路被配置为响应于通过流水线的第一级的第一指令，更新第二记分板以指示该第一目的地寄存器的写暂停。 在第一阶段可能会发出给定指令的重播信号。 响应于第二指令的重放，控制电路被配置为将第二记分板的内容复制到第一记分板。 在各种实施例中，附加记分板可用于检测不同类型的依赖性。

公开(公告)号：US08971329B1

公开(公告)日：2015-03-03

申请号：US12273453

申请日：2008-11-18

Applicant: Randal G. Martin ,  Steven C. Miller ,  Mark D. Stadler ,  David A. Kruckemyer

Inventor： Randal G. Martin ,  Steven C. Miller ,  Mark D. Stadler ,  David A. Kruckemyer

IPC: H04L12/28 ,  H04L12/861

CPC classification number: H04L47/34 ,  H04L45/24 ,  H04L47/10 ,  H04L47/26 ,  H04L47/266 ,  H04L47/39 ,  H04L47/41

Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).

Abstract translation: 多通道数据传输系统（10）包括一个源（12），其生成具有用于在多个请求信道（14）上传送的序列号的数据分组。 数据分组通过多个请求信道（14）通过网络（16）传送到目的地（18）。 目的地（18）响应于序列号，将通过多个请求信道（14）接收的数据分组重新排序成适当的序列，以便于数据处理。 目的地（18）通过多个响应信道（20）向源（12）提供适当的应答分组，以控制来自源（12）的数据分组的流。

公开(公告)号：US08806135B1

公开(公告)日：2014-08-12

申请号：US13250481

申请日：2011-09-30

Applicant: Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

Inventor： Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

IPC: G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.

Abstract translation: 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访​​问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 当错过的加载指令从未完成的负载丢失缓冲区重新发出时，从加载未命中结果缓冲区而不是一级缓存读取错误加载指令的数据。 由于数据存储在加载未命中结果缓冲区中，可能会更改一级缓存中的数据的其他指令不会导致丢失加载指令的数据危险。

公开(公告)号：US08793435B1

公开(公告)日：2014-07-29

申请号：US13250596

申请日：2011-09-30

Applicant: Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

Inventor： Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

IPC: G06F12/10

CPC classification number: G06F12/0897 ,  G06F9/3834 ,  G06F12/084 ,  G06F12/0855

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.

Abstract translation: 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个存储器访问检索多个相关的未完成加载指令的数据，并将数据存储在加载未结果缓冲器中。 加载未结结果缓冲器包括从属数据线，相关数据选择电路，共享数据线和共享数据选择电路。 依赖数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的依赖数据线中。 类似地，共享数据选择电路被配置为从存储器系统中选择数据的子集以存储在相关联的共享数据线中。

公开(公告)号：US06745297B2

公开(公告)日：2004-06-01

申请号：US09829514

申请日：2001-04-09

Applicant: David A. Kruckemyer ,  Joseph B. Rowlands

Inventor： David A. Kruckemyer ,  Joseph B. Rowlands

IPC: G06F1300

CPC classification number: G06F12/0831

Abstract: A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

Abstract translation: 系统可以包括两个或更多个代理，其中至少一些可以缓存数据。 响应于读取事务，缓存代理可以窥探其缓存的数据并在事务的响应阶段中提供响应。 特别地，响应可以包括用于表示该代理内的独占和修改状态的独占指示。 在一个实施例中，响应排他性的代理可负责提供用于读取事务的数据，并且可以发送代理具有与发送数据并发的数据的独占或修改状态中的哪一个的指示。

公开(公告)号：US09280479B1

公开(公告)日：2016-03-08

申请号：US13478100

申请日：2012-05-22

Applicant: David A. Kruckemyer ,  John Gregory Favor ,  Matthew W. Ashcraft

Inventor： David A. Kruckemyer ,  John Gregory Favor ,  Matthew W. Ashcraft

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F9/3824 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2212/1024

Abstract: A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.

Abstract translation: 公开了一种具有增加的吞吐量的存储器系统。 具体来说，存储器系统包括一级写入组合队列，其减少一级缓存和二级缓存之间的数据传输次数。 此外，第二级写入合并缓冲器可以进一步减少存储器系统内的数据传输的数量。 第一级写入组合队列从一级缓存接收数据。 第二级写合并缓冲区从第一级写入组合队列接收数据。 二级缓存从第一级写入组合队列和第二级写入合并缓冲区接收数据。 具体来说，第一级写入组合队列将来自加载存储单元的多个存储事务组合到相关联的地址。 另外，第二级写入合并缓冲区合并来自第一级写入组合队列的数据。

公开(公告)号：US08850121B1

公开(公告)日：2014-09-30

申请号：US13250544

申请日：2011-09-30

Applicant: Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

Inventor： Matthew W. Ashcraft ,  John Gregory Favor ,  David A. Kruckemyer

IPC: G06F12/08

CPC classification number: G06F9/3838 ,  G06F9/30043 ,  G06F9/34

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.

Abstract translation: 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访​​问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 未完成的负载未命中缓冲存储器将第一个缺省加载指令存储在第一个初级条目中。 依赖于第一个错过的加载指令的附加的错过加载指令被存储在第一主入口的相关条目或共享条目中。 如果共享条目用于错过加载指令，则共享条目与主条目相关联。

公开(公告)号：US07437597B1

公开(公告)日：2008-10-14

申请号：US10908586

申请日：2005-05-18

Applicant: David A. Kruckemyer ,  Kevin B. Normoyle ,  Jack H. Choquette

Inventor： David A. Kruckemyer ,  Kevin B. Normoyle ,  Jack H. Choquette

IPC: G06F11/10

CPC classification number: G06F11/1064

Abstract: A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Abstract translation: 回写高速缓存具有存储用于高速缓存行的ECC位的纠错码（ECC）字段。 当检测到ECC错误时，清除缓存行将从内存重新获取。 使用ECC位校正脏高速缓存行，或者发出不可纠正的错误信号。 存储的ECC代码的类型对于干净和脏线是不同的。 清洁线路使用的错误检测代码可以检测到比脏线使用的纠错码更长的多位错误。 脏线使用可以纠正脏线中的位错误的校正代码，而干线的检测代码可能无法更正任何错误。 脏线ECC被优化用于校正，而清洁线的ECC被优化用于检测。 单错误纠正，双错误检测（SECDED）代码可用于脏线，而三重检错码用于干线。

公开(公告)号：US06971038B2

公开(公告)日：2005-11-29

申请号：US10061695

申请日：2002-02-01

Applicant: Sribalan Santhanam ,  Vincent R. von Kaenel ,  David A. Kruckemyer

Inventor： Sribalan Santhanam ,  Vincent R. von Kaenel ,  David A. Kruckemyer

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: A processor may include an execution circuit, an issue circuit coupled to the execution circuit, and a clock tree for clocking circuitry in the processor. The issue circuit issues an instruction to the execution circuit, and generates a control signal responsive to whether or not the instruction is issued to the execution circuit. The execution circuit includes at least a first subcircuit and a second subcircuit. A portion of the clock tree supplies a plurality of clocks to the execution circuit, including at least a first clock clocking the first subcircuit and at least a second clock clocking the second subcircuit. The portion of the clock tree is coupled to receive the control signal for collectively conditionally gating the plurality of clock, and is also configured to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit. A system on a chip may include several processors, and one or more of the processors may be conditionally clocked at the processor level.

Abstract translation: 处理器可以包括执行电路，耦合到执行电路的发行电路，以及用于在处理器中计时电路的时钟树。 发行电路向执行电路发出指令，并且响应于是否向执行电路发出指令而生成控制信号。 执行电路至少包括第一子电路和第二子电路。 时钟树的一部分向执行电路提供多个时钟，包括至少第一时钟计时第一分支电路和至少第二时钟计时第二分支电路。 时钟树的部分被耦合以接收控制信号，用于共同有条件地选通多个时钟，并且还被配置为响应于执行电路的相应子电路中的活动而单独有条件地选择多个时钟中的至少一些。 芯片上的系统可以包括几个处理器，并且一个或多个处理器可以在处理器级别有条件地定时。