公开(公告)号：US07749900B2

公开(公告)日：2010-07-06

申请号：US12242414

申请日：2008-09-30

Applicant: Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

Inventor： Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

IPC: H01L21/02

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/12 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/0029 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract translation: 半导体封装包括可包括芯的半导体衬底。 芯可以包括选自包括陶瓷和玻璃电介质的组中的一种或多种材料。 所述封装还包括设置在所述芯上的一组或多个内部导电元件，设置在所述基板的外侧上的一组或多个外部导电元件的集合，以及半导体管芯，以通过 一个或多个外部导电元件。 芯的示例性材料可以包括氧化铝，氧化锆，碳化物，氮化物，熔融二氧化硅，石英，蓝宝石和派雷克斯中的一种或多种。 可以使用激光器来钻一个或多个电镀通孔，以将内部导电元件耦合到外部导电元件。 介电层可以形成在衬底中以使外部导电元件与芯或内部导电元件绝缘。

公开(公告)号：US20070040204A1

公开(公告)日：2007-02-22

申请号：US11505201

申请日：2006-08-16

Applicant: Markondeya Pulugurtha ,  Devarajan Balaraman ,  Isaac Abothu ,  Rao Tummala ,  Farrokh Ayazi

Inventor： Markondeya Pulugurtha ,  Devarajan Balaraman ,  Isaac Abothu ,  Rao Tummala ,  Farrokh Ayazi

IPC: H01L27/108

CPC classification number: H01L27/1203 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/84 ,  H01L28/55 ,  H01L28/91 ,  H05K1/162 ,  H05K3/243 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2203/0315

Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.

Abstract translation: 公开了高表面电极上的三维电介质结构和制造方法。 示例性结构包括铜箔衬底，形成在衬底上的沟槽电极或高表面积多孔电极结构，在表面上形成的绝缘薄膜，并将箔层压在有机衬底上。 可以使用各种材料来制造包括钛酸钡，钛酸锶，钛酸锶钡（BST），锆钛酸铅（PZT）等周波陶瓷的膜。 其它中间介电常数膜如氧化锌，氮化铝，氮化硅; 典型的顺电介质如氧化钽，氧化铝和二氧化钛。 可以使用溶胶 - 凝胶，水热合成，阳极氧化或气相沉积技术来制造膜。

公开(公告)号：US08456016B2

公开(公告)日：2013-06-04

申请号：US12729821

申请日：2010-03-23

Applicant: Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

Inventor： Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

IPC: H01L23/48

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/12 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/0029 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract translation: 半导体封装包括可包括芯的半导体衬底。 芯可以包括选自包括陶瓷和玻璃电介质的组中的一种或多种材料。 所述封装还包括设置在所述芯上的一组或多个内部导电元件，设置在所述基板的外侧上的一组或多个外部导电元件的集合，以及半导体管芯，以通过 一个或多个外部导电元件。 芯的示例性材料可以包括氧化铝，氧化锆，碳化物，氮化物，熔融二氧化硅，石英，蓝宝石和派雷克斯中的一种或多种。 可以使用激光器来钻一个或多个电镀通孔，以将内部导电元件耦合到外部导电元件。 介电层可以形成在衬底中以使外部导电元件与芯或内部导电元件绝缘。

公开(公告)号：US08174017B2

公开(公告)日：2012-05-08

申请号：US11505201

申请日：2006-08-16

Applicant: Markondeya Raj Pulugurtha ,  Devarajan Balaraman ,  Isaac R. Abothu ,  Rao Tummala ,  Farrokh Ayazi

Inventor： Markondeya Raj Pulugurtha ,  Devarajan Balaraman ,  Isaac R. Abothu ,  Rao Tummala ,  Farrokh Ayazi

IPC: H01L27/108

CPC classification number: H01L27/1203 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/84 ,  H01L28/55 ,  H01L28/91 ,  H05K1/162 ,  H05K3/243 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2203/0315

Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.

Abstract translation: 公开了高表面电极上的三维电介质结构和制造方法。 示例性结构包括铜箔衬底，形成在衬底上的沟槽电极或高表面积多孔电极结构，在表面上形成的绝缘薄膜，并将箔层压在有机衬底上。 可以使用各种材料来制造包括钛酸钡，钛酸锶，钛酸锶钡（BST），锆钛酸铅（PZT）等周波陶瓷的膜。 其它中间介电常数膜如氧化锌，氮化铝，氮化硅; 典型的顺电介质如氧化钽，氧化铝和二氧化钛。 可以使用溶胶 - 凝胶，水热合成，阳极氧化或气相沉积技术来制造膜。

公开(公告)号：US20100289154A1

公开(公告)日：2010-11-18

申请号：US12729821

申请日：2010-03-23

Applicant: Yonggang Li ,  Amruthavalll P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

Inventor： Yonggang Li ,  Amruthavalll P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

IPC: H01L23/48

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/12 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/0029 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

公开(公告)号：US20100078805A1

公开(公告)日：2010-04-01

申请号：US12242414

申请日：2008-09-30

Applicant: Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

Inventor： Yonggang Li ,  Amruthavalli P. Alur ,  Devarajan Balaraman ,  Xiwang Qi ,  Charan K. Gurumurthy

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/12 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/0029 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract translation: 半导体封装包括可包括芯的半导体衬底。 芯可以包括选自包括陶瓷和玻璃电介质的组中的一种或多种材料。 所述封装还包括设置在所述芯上的一组或多个内部导电元件，设置在所述基板的外侧上的一组或多个外部导电元件的集合，以及半导体管芯，以通过 一个或多个外部导电元件。 芯的示例性材料可以包括氧化铝，氧化锆，碳化物，氮化物，熔融二氧化硅，石英，蓝宝石和派雷克斯中的一种或多种。 可以使用激光器来钻一个或多个电镀通孔，以将内部导电元件耦合到外部导电元件。 介电层可以形成在衬底中以使外部导电元件与芯或内部导电元件绝缘。

公开(公告)号：US20060269762A1

公开(公告)日：2006-11-30

申请号：US11363334

申请日：2006-02-27

Applicant: Markondeya Pulugurtha ,  Devarajan Balaraman ,  Rao Tummala ,  Isaac Abothu

Inventor： Markondeya Pulugurtha ,  Devarajan Balaraman ,  Rao Tummala ,  Isaac Abothu

IPC: B32B15/04

CPC classification number: H05K1/162 ,  H01G4/10 ,  H01G4/33 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/121 ,  Y10T428/31678

Abstract: Disclosed are organic-compatible thin film processing techniques with reactive (such as Ti) layers for embedding capacitors into substrates. Hydrothermal synthesis allows direct deposition of high-k films with capacitance density of about 1 μF/cm2 on organic substrates. This is done by reactively growing a high-k film from Ti foil/Ti-coated copper foil/Ti precursor-coated organic substrate in an alkaline barium ion bath. Alternatives may be used to address multiple coatings, low temperature baking, low temperature pyrolysis with oxygen plasma, etc. Sol-gel and RF-sputtering assisted by a reaction with the intermediate layer and a foil transfer process may be used to integrate perovskite thin films with a capacitance in the range of 1-5 μF/cm2. Thermal oxidation of titanium foil/Ti-coated copper foil/Ti-coated organic substrate with a copper conductive layer is also a reactively grown high-k film process for integrating capacitance of hundreds of nF with or without using a foil transfer process.

Abstract translation: 公开了具有用于将电容器嵌入衬底中的反应性（例如Ti）层的有机相容薄膜处理技术。 水热合成允许在有机衬底上直接沉积具有约1μF/ cm 2的电容密度的高k膜。 这是通过在碱性钡离子浴中从Ti箔/ Ti涂覆的铜箔/ Ti前体涂覆的有机衬底上反应生长高k膜而完成的。 替代品可用于处理多层涂料，低温烘烤，氧等离子体的低温热解等。通过与中间层反应和箔转移工艺进行辅助的溶胶 - 凝胶和RF溅射可用于整合钙钛矿薄膜 电容量在1-5μF/ cm 2之间。 具有铜导电层的钛箔/ Ti涂覆的铜箔/ Ti涂覆的有机衬底的热氧化也是用于利用或不使用箔转移工艺来集成数百nF的电容的反应生长的高k膜工艺。