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    Method to form narrow structure using double-damascene process
    1.
    发明授权
    Method to form narrow structure using double-damascene process 有权
    使用双镶嵌工艺形成窄结构的方法

    公开(公告)号：US06355528B1

    公开(公告)日：2002-03-12

    申请号：US09426911

    申请日：1999-10-26

    申请人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

    发明人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

    摘要： A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

    摘要翻译： 在衬底上形成窄槽。 为了形成这样的窄槽，在基板上形成第一材料，第一材料具有侧壁。 形成邻接侧壁的间隔物。 随后，与间隔物相邻地形成第二材料。 去除间隔物，留下第一材料和第二材料之间的凹槽。 在一个实施例中，槽被填充用于诸如门的窄特征的材料，并且第一材料和第二材料被去除。 结果，形成具有由间隔物的宽度限定的长度的门或其他窄特征。 在另一个实施例中，通过小凹槽执行植入物，导致小的局部植入物。

    Very low thermal budget channel implant process for semiconductors
    3.
    发明授权
    Very low thermal budget channel implant process for semiconductors 有权
    用于半导体的非常低的热预算通道注入工艺

    公开(公告)号：US06180468B2

    公开(公告)日：2001-01-30

    申请号：US09177774

    申请日：1998-10-23

    申请人： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

    发明人： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/66537 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

    摘要： An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.

    摘要翻译： 通过使用反向工艺流程为通道注入提供超低热量预算过程，其中形成常规MOS晶体管而不需要沟道注入。 去除原来沉积的多晶硅栅极，使用氮化物膜沉积和蚀刻来形成具有预定配置的氮化物间隔物，并且执行自对准沟道注入。 在通道注入，退火和超退火掺杂之后，去除氮化物间隔物和栅极氧化物，以便随后的第二栅极氧化物的再生长和多晶硅沉积形成第二多晶硅栅极。

    Oxide spacers as solid sources for gallium dopant introduction
    4.
    发明授权
    Oxide spacers as solid sources for gallium dopant introduction 失效
    氧化物间隔物作为镓掺杂剂引入的固体源

    公开(公告)号：US6117719A

    公开(公告)日：2000-09-12

    申请号：US993060

    申请日：1997-12-18

    申请人： Scott Luning ,  Emi Ishida

    发明人： Scott Luning ,  Emi Ishida

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8238

    CPC分类号： H01L29/66492 ,  H01L21/2255 ,  H01L29/1045 ,  H01L29/6659

    摘要： Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

    摘要翻译： 通过从栅电极侧壁间隔物的扩散，在半导体衬底的有源区中形成杂质。 在半导体衬底上形成有栅电介质层的栅电极。 侧壁间隔物形成在栅电极的侧表面上。 随后引入掺杂原子以将间隔物转化为固体掺杂剂源。 掺杂原子从间隔物扩散到半导体衬底中以形成第一掺杂区域。

    Silicidation and deep source-drain formation prior to source-drain extension formation
    5.
    发明授权
    Silicidation and deep source-drain formation prior to source-drain extension formation 失效
    在源极 - 漏极扩展形成之前，硅化和深源 - 漏极形成

    公开(公告)号：US5998272A

    公开(公告)日：1999-12-07

    申请号：US745475

    申请日：1996-11-12

    申请人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

    发明人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

    IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/223 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6659

    摘要： A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.

    摘要翻译： 根据本发明的方法使源极 - 漏极延伸区域暴露的加热步骤的数量最小化，从而使源极 - 漏极延伸区域扩散最小化，并且允许比常规工艺更精确地控制源极 - 漏极扩展区域厚度。 根据本发明，形成邻接栅极的间隔物，然后形成重掺杂的源区和漏区。 栅极和源极和漏极区域被硅化。 随后移除间隔物，然后形成源漏扩展区。 在本发明的一个实施例中，使用激光掺杂工艺来形成源极 - 漏极延伸区域。

    Semiconductor processing employing a semiconductor spacer
    6.
    发明授权
    Semiconductor processing employing a semiconductor spacer 有权
    采用半导体衬垫的半导体处理

    公开(公告)号：US06642134B2

    公开(公告)日：2003-11-04

    申请号：US09401797

    申请日：1999-09-22

    申请人： Emi Ishida ,  Scott Luning

    发明人： Emi Ishida ,  Scott Luning

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/823864 ,  H01L29/6656

    摘要： A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

    摘要翻译： 半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。 半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。 实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

    MOSFET with asymmetrical extension implant
    7.
    发明授权
    MOSFET with asymmetrical extension implant 有权
    具有不对称延伸植入物的MOSFET

    公开(公告)号：US08193592B2

    公开(公告)日：2012-06-05

    申请号：US12904662

    申请日：2010-10-14

    申请人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

    发明人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

    摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

    Stressed field effect transistor and methods for its fabrication
    8.
    发明授权
    Stressed field effect transistor and methods for its fabrication 有权
    强调场效应晶体管及其制造方法

    公开(公告)号：US08148214B2

    公开(公告)日：2012-04-03

    申请号：US12360961

    申请日：2009-01-28

    申请人： Andrew M. Waite ,  Scott Luning

    发明人： Andrew M. Waite ,  Scott Luning

    IPC分类号： H01L21/00

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

    摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

    EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY
    9.
    发明申请
    EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY 有权
    嵌入式硅锗锗排水结构，具有降低的硅胶密封性和接触电阻和增强的通道移动性

    公开(公告)号：US20110062498A1

    公开(公告)日：2011-03-17

    申请号：US12561685

    申请日：2009-09-17

    申请人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

    发明人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

    IPC分类号： H01L29/772 ,  H01L21/335

    CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

    摘要翻译： 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

    Stacking fault reduction in epitaxially grown silicon
    10.
    发明授权
    Stacking fault reduction in epitaxially grown silicon 有权
    堆积外延生长硅中的断层减少

    公开(公告)号：US07893493B2

    公开(公告)日：2011-02-22

    申请号：US11456326

    申请日：2006-07-10

    申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

    发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

    IPC分类号： H01L27/12 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

    摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

    摘要翻译： 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。