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41 条记录 (耗时 0.019 秒)

    Method to form narrow structure using double-damascene process
    1.
    发明授权
    Method to form narrow structure using double-damascene process 有权
    使用双镶嵌工艺形成窄结构的方法

    公开(公告)号：US06355528B1

    公开(公告)日：2002-03-12

    申请号：US09426911

    申请日：1999-10-26

    申请人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

    发明人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

    摘要： A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

    摘要翻译： 在衬底上形成窄槽。 为了形成这样的窄槽，在基板上形成第一材料，第一材料具有侧壁。 形成邻接侧壁的间隔物。 随后，与间隔物相邻地形成第二材料。 去除间隔物，留下第一材料和第二材料之间的凹槽。 在一个实施例中，槽被填充用于诸如门的窄特征的材料，并且第一材料和第二材料被去除。 结果，形成具有由间隔物的宽度限定的长度的门或其他窄特征。 在另一个实施例中，通过小凹槽执行植入物，导致小的局部植入物。

    Semiconductor processing employing a semiconductor spacer
    2.
    发明授权
    Semiconductor processing employing a semiconductor spacer 有权
    采用半导体衬垫的半导体处理

    公开(公告)号：US06642134B2

    公开(公告)日：2003-11-04

    申请号：US09401797

    申请日：1999-09-22

    申请人： Emi Ishida ,  Scott Luning

    发明人： Emi Ishida ,  Scott Luning

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/823864 ,  H01L29/6656

    摘要： A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

    摘要翻译： 半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。 半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。 实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

    Very low thermal budget channel implant process for semiconductors
    4.
    发明授权
    Very low thermal budget channel implant process for semiconductors 有权
    用于半导体的非常低的热预算通道注入工艺

    公开(公告)号：US06180468B2

    公开(公告)日：2001-01-30

    申请号：US09177774

    申请日：1998-10-23

    申请人： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

    发明人： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/66537 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

    摘要： An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.

    摘要翻译： 通过使用反向工艺流程为通道注入提供超低热量预算过程，其中形成常规MOS晶体管而不需要沟道注入。 去除原来沉积的多晶硅栅极，使用氮化物膜沉积和蚀刻来形成具有预定配置的氮化物间隔物，并且执行自对准沟道注入。 在通道注入，退火和超退火掺杂之后，去除氮化物间隔物和栅极氧化物，以便随后的第二栅极氧化物的再生长和多晶硅沉积形成第二多晶硅栅极。

    Oxide spacers as solid sources for gallium dopant introduction
    5.
    发明授权
    Oxide spacers as solid sources for gallium dopant introduction 失效
    氧化物间隔物作为镓掺杂剂引入的固体源

    公开(公告)号：US6117719A

    公开(公告)日：2000-09-12

    申请号：US993060

    申请日：1997-12-18

    申请人： Scott Luning ,  Emi Ishida

    发明人： Scott Luning ,  Emi Ishida

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8238

    CPC分类号： H01L29/66492 ,  H01L21/2255 ,  H01L29/1045 ,  H01L29/6659

    摘要： Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

    摘要翻译： 通过从栅电极侧壁间隔物的扩散，在半导体衬底的有源区中形成杂质。 在半导体衬底上形成有栅电介质层的栅电极。 侧壁间隔物形成在栅电极的侧表面上。 随后引入掺杂原子以将间隔物转化为固体掺杂剂源。 掺杂原子从间隔物扩散到半导体衬底中以形成第一掺杂区域。

    Silicidation and deep source-drain formation prior to source-drain extension formation
    6.
    发明授权
    Silicidation and deep source-drain formation prior to source-drain extension formation 失效
    在源极 - 漏极扩展形成之前，硅化和深源 - 漏极形成

    公开(公告)号：US5998272A

    公开(公告)日：1999-12-07

    申请号：US745475

    申请日：1996-11-12

    申请人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

    发明人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

    IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/223 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6659

    摘要： A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.

    摘要翻译： 根据本发明的方法使源极 - 漏极延伸区域暴露的加热步骤的数量最小化，从而使源极 - 漏极延伸区域扩散最小化，并且允许比常规工艺更精确地控制源极 - 漏极扩展区域厚度。 根据本发明，形成邻接栅极的间隔物，然后形成重掺杂的源区和漏区。 栅极和源极和漏极区域被硅化。 随后移除间隔物，然后形成源漏扩展区。 在本发明的一个实施例中，使用激光掺杂工艺来形成源极 - 漏极延伸区域。

    Source/drain doping technique for ultra-thin-body SOI MOS transistors
    8.
    发明授权
    Source/drain doping technique for ultra-thin-body SOI MOS transistors 有权
    超薄体SOI MOS晶体管的源极/漏极掺杂技术

    公开(公告)号：US06403433B1

    公开(公告)日：2002-06-11

    申请号：US09397217

    申请日：1999-09-16

    申请人： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

    发明人： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/78618

    摘要： An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

    摘要翻译： 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。 在掺杂之前，升高的源极和漏极区非晶化。 中性离子物质可用于使提升的源极和漏极区域非晶化。 掺杂剂在低温快速热退火工艺中被激活。

    Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes
    9.
    发明授权
    Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes 有权
    具有均匀的，完全掺杂的栅电极的半导体器件的制造方法

    公开(公告)号：US06277698B1

    公开(公告)日：2001-08-21

    申请号：US09382580

    申请日：1999-08-25

    申请人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

    发明人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

    IPC分类号： H01L21336

    CPC分类号： H01L29/66583 ,  H01L21/823842

    摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

    摘要翻译： 通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。 对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。 然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

    Deuterium doping for hot carrier reliability improvement
    10.
    发明授权
    Deuterium doping for hot carrier reliability improvement 失效
    氘掺杂热载体可靠性提高

    公开(公告)号：US6143632A

    公开(公告)日：2000-11-07

    申请号：US993049

    申请日：1997-12-18

    申请人： Emi Ishida ,  Peng Fang

    发明人： Emi Ishida ,  Peng Fang

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L29/32 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

    CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/32 ,  H01L29/4983 ,  H01L29/518

    摘要： A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and a topside protective dielectric layer deposited thereon. Deuterium is introduced to the semiconductor device by using deuterium-containing reactants in at least one of the semiconductor manufacturing steps to passivate dangling silicon bonds at the silicon/oxide interface region.

    摘要翻译： 具有减少的热载流子劣化的半导体器件通过用氘掺杂半导体衬底和栅极氧化物来实现。 常规的半导体器件形成有顺序沉积的金属层和介电层以及沉积在其上的顶侧保护电介质层。 通过在半导体制造步骤中的至少一个中使用含氘的反应物，在硅/氧化物界面区域钝化悬挂的硅键，将氘引入半导体器件。