公开(公告)号：US4229755A

公开(公告)日：1980-10-21

申请号：US934223

申请日：1978-08-15

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L27/112 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823456 ,  H01L21/033 ,  H01L21/8236 ,  H01L27/0251

摘要： A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices composed of a variable threshold memory device having a thin silicon dioxide gate insulator in combination with a pair of fixed threshold devices having a thicker silicon dioxide gate insulator arranged with a common silicon nitride layer and common gate electrode. The additional fixed threshold peripheral transistors are fabricated without a silicon nitride layer. In addition, the method contains no processing steps subsequent to the fabrication of the PDS devices which necessitate the application of temperatures in excess of 900.degree. C.

摘要翻译： 一种制造包括N沟道硅栅极非易失性存储器元件和附加外围晶体管元件的大规模集成电路的方法。 非易失性存储器元件被制造为PDS保护的漏极 - 源极器件，其由具有薄的二氧化硅栅极绝缘体的可变阈值存储器件组成，所述可变阈值存储器件与一对具有较厚的二氧化硅栅极绝缘体的固定阈值器件组合， 和共栅极。 附加的固定阈值外围晶体管是在没有氮化硅层的情况下制造的。 此外，该方法在制造需要超过900℃的温度的PDS装置之后不包含加工步骤。

公开(公告)号：US4990983A

公开(公告)日：1991-02-05

申请号：US130914

申请日：1987-12-07

申请人： Frank Z. Custode ,  John G. Poksheva

发明人： Frank Z. Custode ,  John G. Poksheva

IPC分类号： H01L21/762 ,  H01L27/092

CPC分类号： H01L21/76216 ,  H01L27/0928 ,  Y10S257/906

摘要： The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET.

摘要翻译： 围绕NMOS器件的场氧化物或NMOS器件周围的场氧化物以及CMOS中的NMOS和PMOS器件之间的场氧化物被分裂或切口以形成至少一个薄场氧化物区域，在衬底中形成退化P +区以增加 不需要的场氧化物FET的阈值电压。

公开(公告)号：US4947225A

公开(公告)日：1990-08-07

申请号：US73591

申请日：1987-07-15

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/78

摘要： The invention provides a sub-micron MOS device and process for manufacturing with contacts down to 0.1 microns. It also provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns. Further, there is provided a sub-micron bipolar device of a type having emitter, base and collector adjacent each other rather than in surrounding relationship, together with contacts down to 0.1 micron and process for making the same. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and some convert polysilicon to polyoxide, except where protected by nitride buttons over the electrodes to prevent oxidation of the polysilicon therebeneath. One embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG. In the polysilicon oxidized devices, the contacts may be made oversized to compensate for irregularities in processing.

摘要翻译： 本发明提供了一种亚微米MOS器件和用于制造具有低至0.1微米的触点的工艺。 它还提供了一种亚微米双极器件及其制造方法，该触点具有低至0.1微米的触点。 此外，提供了一种类型的亚微米双极器件，其具有发射极，基极和集电极彼此相邻而不是周围的关系，以及低至0.1微米的触点及其制造方法。 所有工艺和器件都使用掺杂多晶硅作为器件元件的电极，有些将多晶硅转化为多氧化物，除了在电极上用氮化物按钮保护以防止其下面的多晶硅氧化之外。 一个实施例用SOG覆盖的低温氧化物围绕多晶硅接触。 在多晶硅氧化器件中，可以使触点尺寸过大以补偿加工中的凹凸。

公开(公告)号：US4994407A

公开(公告)日：1991-02-19

申请号：US247053

申请日：1988-09-20

申请人： Frank Z. Custode ,  John G. Poksheva

发明人： Frank Z. Custode ,  John G. Poksheva

IPC分类号： H01L21/762 ,  H01L27/092

CPC分类号： H01L21/76216 ,  H01L27/092 ,  Y10S438/953 ,  Y10S438/981

摘要： The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET.

公开(公告)号：US4694565A

公开(公告)日：1987-09-22

申请号：US856304

申请日：1986-04-28

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/385 ,  H01L21/425

CPC分类号： H01L21/762 ,  H01L21/823871 ,  Y10S438/953

摘要： The invention provides a novel high speed hardened CMOS structure and process for developing the structure. In a first embodiment, the surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no transition from the plane to the plane. In a first embodiment, one of the gate electrode overlaps is avoided, thereby eliminating the sidewalk effect or parasitic device from causing leakage on that side of the channel. The preferred embodiment provides a device with no field oxide extending into the silicon wafer and with no overlap of the gate electrode over the field oxide. This is achieved by causing the gate metal interconnect to proceed linearly along the active region over either the source or drain before it leaves the active region, thereby avoiding the establishing of an extra field in the gate region. An alternative method for accomplishing the foregoing is to provide double metal layers and allow the gate metal interconnect to leave the active area directly from the gate electrode because the spacing is sufficient to render the metal interconnect field ineffective to cause parasitic problems; also, in this embodiment the metal interconnect can be run linearly along the active region and depart the same over the source or drain thereby even decreasing gate capacitance effects. A method for establishing sub-micron contacts is disclosed which permits manufacture of the CMOS devices to sub-micron dimensions.

摘要翻译： 本发明提供了一种用于开发结构的新型高速硬化CMOS结构和工艺。 在第一实施例中，通过在该表面上建立场氧化物，硅晶片的<100>表面保持完整，因此不存在从<100>平面到<111>平面的转变。 在第一实施例中，避免了栅电极重叠中的一个，从而消除了人行道效应或寄生装置在通道的该侧上的泄漏。 优选实施例提供一种没有场氧化物的器件延伸到硅晶片中，并且在场氧化物上没有栅电极的重叠。 这是通过使栅极金属互连在离开有源区之前在源极或漏极上沿着有源区线性地进行，从而避免在栅极区域中建立额外的场。 实现上述目的的替代方法是提供双金属层，并允许栅极金属互连直接从栅电极离开有源区，因为间隔足以使金属互连场无效以引起寄生问题; 此外，在该实施例中，金属互连可以沿有源区线性地运行并且在源极或漏极上偏离，从而甚至降低栅极电容效应。 公开了一种用于建立亚微米接触的方法，其允许将CMOS器件制造成亚微米尺寸。

公开(公告)号：US4406049A

公开(公告)日：1983-09-27

申请号：US397647

申请日：1982-07-12

申请人： Matthias L. Tam ,  Frank Z. Custode

发明人： Matthias L. Tam ,  Frank Z. Custode

IPC分类号： H01L21/8246 ,  H01L23/535 ,  H01L27/112 ,  H01L29/08 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L27/11226 ,  H01L23/535 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/0847 ,  H01L2924/0002

摘要： The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is achieved by a mask which permits doping of the source and drain regions to comprise FETs for the cells indicative of one state of logic while precluding doping of the source and drain regions to complete the channel in the cells comprising the other state of logic. Also, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells. The process simplifies the number of steps required to manufacture the FETs and non-FETs by simply providing the programming after the basic cells are formed. Such unprogrammed structures may be inventoried and simply programmed i.e. completed by selective doping and establishing of contacts to fulfill orders to customer specifications immediately.

摘要翻译： 本发明通过采用根据编程的FET或非FET的ROM单元节省存储器空间。 每个单元包括栅极，源极和漏极区域，并且用于连接到位线和字线。 通过掩模实现编程，该掩模允许源极和漏极区域的掺杂以包括用于指示一种逻辑状态的电池的FET，同时排除源极和漏极区域的掺杂以在包括另一逻辑状态的电池中完成通道。 此外，制造FET，它们的触点在优选地是扩散线的位线之间线性延伸，并且字线与线性单元的栅极直接接触。 该过程通过在形成基本单元之后简单地提供编程来简化制造FET和非FET的步骤数量。 这样的未编程结构可以被盘点并简单地编程，即通过选择性掺杂和建立触点来立即完成对客户规格的订单。

公开(公告)号：US4404581A

公开(公告)日：1983-09-13

申请号：US216578

申请日：1980-12-15

申请人： Matthias L. Tam ,  Frank Z. Custode

发明人： Matthias L. Tam ,  Frank Z. Custode

IPC分类号： G11C17/00 ,  G11C17/16 ,  H01L21/8246 ,  H01L27/06 ,  H01L27/112 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L29/04 ,  H01L29/12 ,  H01L27/02

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L27/0688 ,  H01L29/0847 ,  H01L29/456

摘要： The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

摘要翻译： 本发明包括在其未掺杂多晶硅的漏极引线中具有电阻器的唯一FET，其特征在于当FET导通时在FET和电阻器两端不施加偏置电压时具有高电阻，该偏置电压不可逆地改变 该电阻器具有高的导通状态，从而选择性地提供两个逻辑状态。 该设备可以包括用于ROM存储器的冗余单元，并且可以使用VLSI MOS处理步骤独特地制造以提供新的制造过程。

公开(公告)号：US5114874A

公开(公告)日：1992-05-19

申请号：US529982

申请日：1990-05-30

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/78 ,  Y10S148/02

摘要： The sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts provide sub-micron devices and processes for manufacturing them with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG which avoids all oxidation steps that could be detrimental in this contact size range. An optional alternative includes large contact area enlarging layers of silicide directly beneath each contact.

摘要翻译： 具有用于形成亚微米触点的方法的亚微米NMOS，PMOS和CMOS器件提供亚微米器件和用于制造具有低于0.1微米或更小的触点的工艺。 所有的工艺和器件都使用掺杂的多晶硅作为器件元件的电极，优选的实施方案是用SOG覆盖的低温氧化物围绕多晶硅接触，避免了在该接触尺寸范围内可能是有害的所有氧化步骤。 可选的替代方案包括在每个接触件正下方的大的接触面积放大的硅化物层。

公开(公告)号：US5114867A

公开(公告)日：1992-05-19

申请号：US583251

申请日：1990-09-17

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/78

摘要： The sub-micron bipolar devices with method for forming sub-micron contacts provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG to avoid all oxidation steps which otherwise might be detrimental to the extremely thin whisker contacts.

摘要翻译： 具有形成亚微米触点的方法的亚微米双极器件提供亚微米双极器件和用于制造具有低至0.1微米或更小的触点的工艺。 所有的工艺和器件都使用掺杂的多晶硅作为器件元件的电极，而优选实施例用SOG覆盖的低温氧化物围绕多晶硅接触，以避免所有的氧化步骤，否则可能对极细的晶须接触是有害的。

公开(公告)号：US4749662A

公开(公告)日：1988-06-07

申请号：US837560

申请日：1986-03-03

申请人： Frank Z. Custode

发明人： Frank Z. Custode

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823871 ,  H01L21/76218 ,  H01L21/823807 ,  H01L21/823878

摘要： The present invention is a CMOS process for forming an N-channel device and a P-channel device on a doped substrate wherein an active region surrounded by field for the N-channel device is delineated to comprise a thin layer of oxide, a layer of nitride and a further layer of oxide. An active region surrounded by field of the P-channel device is delineated to comprise a thin layer of oxide and a layer of nitride. A well beneath the P-channel active region and the surrounding field region therefor is implanted. Then, the N-channel field is implanted. The oxide layer is removed from the N-channel active region and field oxide is grown for both channels while the well implant and the field implant are concurrently driven-in. The nitride layers are removed, and sacrificial oxide is grown and removed. Implanting is carried out for threshold adjust. The gate oxide is grown, and the gate electrodes of doped polysilicon are delineated for each channel. An activated source and drain is established for each channel. The crossover oxide is deposited, and metal contacts are established to each source and drain and to the gate polysilicon through the crossover oxide.

摘要翻译： 本发明是用于在掺杂衬底上形成N沟道器件和P沟道器件的CMOS工艺，其中被N沟道器件的场包围的有源区域被描绘为包括薄层氧化层， 氮化物和另一层氧化物。 描绘由P沟道器件的场围绕的有源区域，以包括氧化物薄层和氮化物层。 植入P沟道活性区及其周围场区以下的阱。 然后，植入N沟道场。 从N沟道有源区域去除氧化物层，并且对于两个沟道生长场氧化物，同时井注入和场植入物同时被驱入。 去除氮化物层，生长和除去牺牲氧化物。 进行植入以进行阈值调整。 生长栅极氧化物，并且为每个沟道描绘掺杂多晶硅的栅电极。 为每个通道建立一个激活的源极和漏极。 沉积交叉氧化物，并且通过交叉氧化物将金属接触建立到每个源极和漏极以及栅极多晶硅。