公开(公告)号：US20250169087A1

公开(公告)日：2025-05-22

申请号：US18512859

申请日：2023-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. Holt ,  Crystal R. Kenney ,  Vibhor Jain ,  John J. Pekarik ,  Mona Nafari ,  Jeffrey B. Johnson

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base above the collector region; an emitter above the intrinsic base region; and an extrinsic base on the intrinsic base and adjacent to the emitter, wherein the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region.

公开(公告)号：US20250159999A1

公开(公告)日：2025-05-15

申请号：US18388441

申请日：2023-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Uppili S. Raghunathan ,  Rajendran Krishnasamy ,  Sagar Premnath Karalkar ,  Alexander M. Derrickson ,  Vibhor Jain

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.

公开(公告)号：US20250151369A1

公开(公告)日：2025-05-08

申请号：US18501170

申请日：2023-11-03

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan

IPC: H01L29/51 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H10B53/30

Abstract: Structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device. The structure comprises a first electrode including a first doped region in a semiconductor layer and a second doped region in the semiconductor layer, an interconnection that is configured to connect the first doped region to the second doped region, a ferroelectric layer on the semiconductor layer, and a second electrode including a first section and a second section on the ferroelectric layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material.

公开(公告)号：US20250149499A1

公开(公告)日：2025-05-08

申请号：US18504526

申请日：2023-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ravi Prakash SRIVASTAVA ,  Matthew Charles GORFIEN

IPC: H01L23/00

Abstract: A method for hybrid bonding a first semiconductor substrate to a second semiconductor substrate includes forming a first plurality of metal pads on a face of the first substrate, forming a second plurality of metal pads on a face of the second substrate, selectively forming a first dielectric layer over a first insulating material of the first substrate, selectively forming a second dielectric layer over a second insulating material of the second substrate, placing the face of the first substrate against the face of the second substrate so that the first dielectric layer contacts the second dielectric layer, and heating the first substrate and the second substrate to bond the first plurality of metal pads to the second plurality of metal pads. The first and second dielectric layers may be formed by an area selective deposition process.

公开(公告)号：US20250148181A1

公开(公告)日：2025-05-08

申请号：US18503212

申请日：2023-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bradley A. Orner ,  Romain H.A. Feuillette ,  Vivienne A.B. Miller ,  Petar Ivanov Todorov ,  Stephen T. Burgess

IPC: G06F30/3308 ,  G02B27/00

Abstract: Disclosed are a photonic integrated circuit (PIC) design system and method including optical signal propagation simulation with coupling awareness to account for transition loss due to a difference between at least one specific physical parameter (e.g., curvature radius, material composition, etc.) in optically coupled photonic devices. Coupling awareness can be achieved by including, within a bus of a netlist between the photonic devices, at least one pair of physical data pins: one associated with a specific physical parameter in the light emitting photonic device and the other associated with the specific physical parameter in the light receiving photonic device. Alternatively, coupling awareness can be achieved by running a utility to identify a parameter mismatch between the light emitting and receiving photonic devices, developing a custom coupling cell to account for the mismatch, and inserting the custom coupling cell into a design layout for the PIC.

公开(公告)号：US20250147235A1

公开(公告)日：2025-05-08

申请号：US18501602

申请日：2023-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Andreas D. Stricker ,  Abdelsalam Aboketaf ,  Judson R. Holt ,  Kevin K. Dezfulian ,  Kenneth J. Giewont ,  Alexander Derrickson ,  Won Suk Lee ,  Sujith Chandran ,  Ryan W. Sporer ,  Teng-Yin Lin

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector that is disposed on a substrate and that includes a light-absorbing layer. The light-absorbing layer includes a sidewall and a notch in the sidewall. The structure further comprises a waveguide core including a section adjacent to the notch in the sidewall of the light-absorbing layer.

公开(公告)号：US12292470B2

公开(公告)日：2025-05-06

申请号：US18172488

申请日：2023-02-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Yunyao Jiang

IPC: G01R31/28 ,  G02B6/12

Abstract: A structure provides a defect sensor for a cavity in an integrated circuit (IC). The structure includes a cavity defined in a substrate. A boundary is located where the cavity meets with a cavity-free area of the substrate. A metal line is arranged in a serpentine path in both a vertical and a horizontal direction and crosses the boundary. A controller may be provided that is configured to, in response to a change in an electrical characteristic of a signal through the metal line, generate an indication of the presence of a defect and/or change operation of at least one component of the IC. The structure may find application relative to a photonics integrated circuit (PIC) structure including an optical waveguide with a cavity under the optical waveguide.

公开(公告)号：US20250140599A1

公开(公告)日：2025-05-01

申请号：US18385268

申请日：2023-10-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jacob M. DeAngelis ,  Trevor S. Wills ,  Mark D. Levy ,  Spencer H. Porter ,  Brett T. Cucci ,  Rajendran Krishnasamy

IPC: H01L21/762 ,  H01L29/04 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with isolation structures and methods of manufacture. The structure includes: a stack of semiconductor materials; a semiconductor substrate under the stack of semiconductor materials; a trench filled with in insulator material; and a damaged region of the stack of semiconductor materials extending from at least a bottom of the insulator material to the semiconductor substrate.

公开(公告)号：US12288782B2

公开(公告)日：2025-04-29

申请号：US17679655

申请日：2022-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Juhan Kim ,  Sangmoon J. Kim ,  Mahbub Rashed ,  Navneet K. Jain

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

公开(公告)号：US12284924B2

公开(公告)日：2025-04-22

申请号：US17697974

申请日：2022-03-18

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lup San Leong ,  Juan Boon Tan ,  Benfu Lin ,  Yi Jiang

IPC: H10N70/00 ,  H10B63/00

Abstract: According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.