公开(公告)号：US20060036808A1

公开(公告)日：2006-02-16

申请号：US11214466

申请日：2005-08-29

申请人： Gideon Intrater ,  Anders Jagd ,  Ryan Kinter

发明人： Gideon Intrater ,  Anders Jagd ,  Ryan Kinter

IPC分类号： G06F12/00

CPC分类号： G06F9/3812 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0848

摘要： A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing. If the access is redirected, the access to the instruction memory is performed by the instruction memory interface, and data retrieved by the instruction memory interface is then provided to the data memory interface, and in turn to the pipeline stage within the processing system that requested the data memory interface to access the data.

公开(公告)号：US20050102483A1

公开(公告)日：2005-05-12

申请号：US11003120

申请日：2004-12-03

申请人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

发明人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0684

摘要： The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

摘要翻译： 本发明包括一种调试嵌入式处理器的方法。 访问嵌入式处理器的便携式存储器以形成表征便笺式存储器的暂存区域区域的配置的配置文件。 嵌入式处理器使用配置文件中的信息进行调试。 本发明还包括具有连接到处理器核心的处理器核心和临时存储器存储器的嵌入式处理器。 便笺本式存储器包括一组暂存区域。 临时存储器存储表征该组暂存区区域的基址和区域大小值的值。

公开(公告)号：US5603017A

公开(公告)日：1997-02-11

申请号：US309546

申请日：1994-09-20

申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5566308A

公开(公告)日：1996-10-15

申请号：US248769

申请日：1994-05-25

申请人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

发明人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/00

CPC分类号： G06F9/342 ,  G06F9/32 ,  G06F9/321

摘要： A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

摘要翻译： 处理器核心，用于提供微处理器的可寻址存储空间的线性扩展，同时具有最小的附加硬件和软件复杂性。 N + x位指针寄存器（例如程序计数器）保存N + x位指令地址。 N + x位指令地址向执行单元提供指向由执行单元处理的存储器中的指令的指针。 编码器将N + x位地址编码为N + x位地址的N位编码。 因此，处理器核可以处理比2N多两倍的存储单元。 另外两个寄存器分别保存数据地址的一部分（即指向要操作的存储器中的基准的指针）。 地址前缀将两个寄存器中地址的部分连接起来形成数据地址。 因此，地址由存储在多个寄存器中的数据地址的部分形成，而不对这些部分执行任何算术。

公开(公告)号：US5630153A

公开(公告)日：1997-05-13

申请号：US317783

申请日：1994-10-04

申请人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

发明人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

IPC分类号： G06J3/00 ,  G06F9/38 ,  G06F15/78 ,  H04L27/00 ,  H04M11/00 ,  H04N1/40 ,  G06F9/26 ,  G06F9/40 ,  G06F9/44 ,  G06F13/36

CPC分类号： H04L27/00 ,  G06F15/7842 ,  G06F9/3885

摘要： An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

摘要翻译： 一种用于处理包括通用处理器和数字信号处理器（DSP）模块的数字信号的集成数据处理平台。 DSP模块利用通用处理器选择的一系列DSP操作，从数字信号中恢复数字数据。 通用处理器处理由DSP模块恢复的数字数据，但也可用于执行通用任务。 共享内部存储器阵列选择性地向DSP模块和通用处理器提供信息。 存储在内部存储器阵列中的信息包括在DSP算法的执行中使用的操作数和通用CPU所使用的选择的指令和数据，用于控制DSP算法的执行或用于执行其自己的通用任务。 在许多应用中，数据处理系统将包括模拟前端，将模拟传输通道上接收的调制输入信号转换为相应的数字信号，以供数据处理系统处理，数据处理系统也可以直接接收数字信号 从数字来源。

公开(公告)号：US5249286A

公开(公告)日：1993-09-28

申请号：US982031

申请日：1992-11-24

申请人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

发明人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

摘要翻译： 一种微处理器架构，其包括将单个条目锁定到其集成指令高速缓存和数据高速缓存中的能力，同时使缓存的其余部分被解锁并可用于捕获微处理器的动态参考位置。 微处理器还包括锁定指令高速缓存条目的能力，而不需要在锁定过程期间执行指令。

公开(公告)号：US08145882B1

公开(公告)日：2012-03-27

申请号：US11442696

申请日：2006-05-25

申请人： Karagada Ramarao Kishore ,  Gideon Intrater ,  Xing Xu Jiang ,  Maria Ukanwa

发明人： Karagada Ramarao Kishore ,  Gideon Intrater ,  Xing Xu Jiang ,  Maria Ukanwa

IPC分类号： G06F15/16

CPC分类号： G06F15/78 ,  G06F9/30181 ,  G06F15/16

摘要： A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An interface is positioned between the main processing core and the user execution block. A computer readable medium includes executable instructions to describe a processing core supporting execution of a proprietary instruction set and decoding of customized instructions that adhere to a specified pattern. The specified pattern includes a source, a destination and a latency period. A user execution block is connected to the processing core to execute the customized instructions.

摘要翻译： 在硬件中实现的系统包括用于无序执行的主处理核心解码指令。 说明包括基于模板的用户定义的指令。 用户执行块执行基于模板的用户定义的指令。 接口位于主处理核心和用户执行块之间。 计算机可读介质包括可执行指令，用于描述支持专有指令集的执行的处理核心以及遵循指定模式的定制指令的解码。 指定的模式包括源，目的地和等待时间。 用户执行块连接到处理核心以执行定制指令。

公开(公告)号：US5872960A

公开(公告)日：1999-02-16

申请号：US624879

申请日：1996-03-27

申请人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

发明人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5638306A

公开(公告)日：1997-06-10

申请号：US583538

申请日：1996-01-05

申请人： Gideon Intrater ,  Oved Oz ,  Alberto Sandbank

发明人： Gideon Intrater ,  Oved Oz ,  Alberto Sandbank

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes test hook functions for facilitating production testing of the system.

摘要翻译： 本发明涉及集成数据处理系统的各种特征，其包括用于根据GP指令集处理数据的通用（GP）CPU核和用于根据命令处理数据的数字信号处理器（DSP）模块 列表代码 DSP模块可操作以独立于执行由CPU核心的GP指令集执行的命令列表代码。 该系统还包括用于促进系统的生产测试的测试钩功能。

公开(公告)号：US5613149A

公开(公告)日：1997-03-18

申请号：US546187

申请日：1995-10-20

申请人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

发明人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00 ,  G06F15/16

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal. The input port is connected to provide the output of the comparator as the input data signal to the central processing unit.

摘要翻译： 用于识别模拟信号的值的集成电路结构包括执行指令以执行数据处理操作的中央处理单元。 数据处理操作包括逐次近似模拟对话转换操作，以基于输入数据信号提供数字值。 具有调制（PWM）元件的脉冲将数字值转换成具有对应于数字值的占空比的方波输出信号。 PWM元件适于连接到低通滤波器，使得方波输出信号被提供为低通滤波器的输入。 低通滤波器提供与方波输出信号的占空比对应的输出模拟信号。 输入端口适于连接到比较器的输出。 比较器接收低通滤波器和模拟信号的输出模拟信号作为输入。 连接输入端口，将比较器的输出作为输入数据信号提供给中央处理单元。