公开(公告)号：US06762067B1

公开(公告)日：2004-07-13

申请号：US09487969

申请日：2000-01-18

申请人： Maria Clemens Y. Quinones ,  Gilmore S. Baje ,  Maria Christina B. Estacio ,  Marvin R. Gestole ,  Oliver M. Ledon ,  Santos E. Mepieza

发明人： Maria Clemens Y. Quinones ,  Gilmore S. Baje ,  Maria Christina B. Estacio ,  Marvin R. Gestole ,  Oliver M. Ledon ,  Santos E. Mepieza

IPC分类号： H01L2148

CPC分类号： H01L23/488 ,  H01L23/49562 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73263 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/19043 ,  Y10T29/49121 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies therebetween and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.

摘要翻译： 一种用于封装多个芯片器件的方法和装置。 该方法包括提供多个与导轨结合在一起的底部引线框架，以形成底部引线框架组件，并提供多个与导轨结合在一起的顶部引线框架，以形成顶部引线框架组件。 模具放置在顶部和底部引线框架之间，并且顶部和底部引线框架组件彼此耦合。 模具附接到底部引线框架的管芯附接焊盘，并且用焊料凸块连接到顶部引线框架。 将模制体放置在顶部和底部引线框周围，其中模具在其间并且导轨从顶部引线框架和底部引线框架移除，从而提供多个芯片装置。

公开(公告)号：US06423623B1

公开(公告)日：2002-07-23

申请号：US09141184

申请日：1998-08-27

申请人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

发明人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

摘要翻译： 一种显着降低封装电阻的封装技术。 根据本发明，封装外部的引线框架与封装模制件内的硅芯片表面上的焊球直接接触，消除了电阻线互连。 本发明的封装技术特别适用于功率晶体管。