Low-resistance electrode design
    1.
    发明授权
    Low-resistance electrode design 有权
    低电阻电极设计

    公开(公告)号:US08846473B2

    公开(公告)日:2014-09-30

    申请号:US13458213

    申请日:2012-04-27

    Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    Abstract translation: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    Radio-frequency switch circuit with separately controlled shunt switching device
    2.
    发明授权
    Radio-frequency switch circuit with separately controlled shunt switching device 有权
    射频开关电路具有独立控制的分流开关装置

    公开(公告)号:US08299835B2

    公开(公告)日:2012-10-30

    申请号:US12364140

    申请日:2009-02-02

    CPC classification number: H03K17/063 H03K2017/066

    Abstract: A switch circuit is provided that includes at least one main switching device and at least one shunt switching device. Each main switching device is connected in series with a conductor that carries an RF signal between an input circuit and an output circuit. Each shunt switching device is connected between a controlling terminal of the main switching device and a high frequency ground. The switch circuit can provide substantially improved OFF state isolation over other approaches.

    Abstract translation: 提供一种开关电路,其包括至少一个主开关装置和至少一个分流开关装置。 每个主开关装置与在输入电路和输出电路之间承载RF信号的导体串联连接。 每个分流开关装置连接在主开关装置的控制端子和高频接地之间。 与其他方法相比,开关电路可以提供显着改进的OFF状态隔离。

    Low-Resistance Electrode Design
    3.
    发明申请
    Low-Resistance Electrode Design 有权
    低电阻电极设计

    公开(公告)号:US20120216161A1

    公开(公告)日:2012-08-23

    申请号:US13458213

    申请日:2012-04-27

    Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    Abstract translation: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR
    4.
    发明申请
    ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR 有权
    增强型绝缘栅结构场效应晶体管

    公开(公告)号:US20080203430A1

    公开(公告)日:2008-08-28

    申请号:US11781338

    申请日:2007-07-23

    CPC classification number: H01L29/7783 H01L29/2003 H01L29/402

    Abstract: Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

    Abstract translation: 本发明的方面提供了一种在零栅极偏压,低栅极电流和/或高可靠性下具有低功耗的增强模式(E模式)绝缘栅(IG)双异质结构场效应晶体管(DHFET)。 根据本发明的实施例的E型HFET包括:顶部和底部阻挡层; 以及夹在底部和顶部阻挡层之间的沟道层,其中底部和顶部势垒层具有比沟道层更大的带隙,并且其中底部势垒层的极化电荷消耗沟道层和顶部势垒的极化电荷 层在沟道层中诱导载流子; 并且其中底部阻挡层中的总极化电荷大于顶部势垒层中的总极化电荷,使得沟道层在零栅极偏压下基本上耗尽。

    Device and circuit with improved linearity
    5.
    发明授权
    Device and circuit with improved linearity 有权
    器件和电路具有提高的线性度

    公开(公告)号:US08643430B2

    公开(公告)日:2014-02-04

    申请号:US13311633

    申请日:2011-12-06

    CPC classification number: H03H5/12

    Abstract: A solution for compensating intermodulation distortion of a component is provided. A circuit element includes multiple connected components. At least two of the connected components comprise current-voltage characteristics of opposite signs (e.g., sublinear and superlinear current-voltage characteristics) such that the current-voltage characteristics of the circuit element produces a level of intermodulation distortion for the circuit element lower than a level of intermodulation distortion for each of the connected components.

    Abstract translation: 提供了用于补偿组件的互调失真的解决方案。 电路元件包括多个连接的部件。 连接的组件中的至少两个包括具有相反符号的电流 - 电压特性(例如,亚线性和超级线性电流 - 电压特性),使得电路元件的电流 - 电压特性产生电路元件的互调失真水平低于 每个连接组件的互调失真水平。

    Composite contact for semiconductor device
    7.
    发明授权
    Composite contact for semiconductor device 有权
    半导体器件的复合接点

    公开(公告)号:US08461631B2

    公开(公告)日:2013-06-11

    申请号:US11781302

    申请日:2007-07-23

    Abstract: A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.

    Abstract translation: 提供了一种用于半导体器件的复合触点。 复合触点包括附接到器件中的半导体层的直流导电电极和部分地在直流导电电极上并延伸超过直流导电电极的电容电极。 复合触点提供与半导体层的组合的电阻 - 电容耦合。 结果,当对应的半导体器件以高频率操作时,接触阻抗减小。

    Parameter extraction using radio frequency signals
    8.
    发明授权
    Parameter extraction using radio frequency signals 有权
    使用射频信号进行参数提取

    公开(公告)号:US08395392B2

    公开(公告)日:2013-03-12

    申请号:US12646121

    申请日:2009-12-23

    CPC classification number: G01R31/2648

    Abstract: A set of parameters of an evaluation structure are extracted by applying a radio frequency (RF) signal through a first capacitive contact and a second capacitive contact to the evaluation structure. Measurement data corresponding to an impedance of the evaluation structure is acquired while the RF signal is applied, and the set of parameters are extracted from the measurement data. In an embodiment, multiple pairs of capacitive contacts can be utilized to acquire measurement data. Each pair of capacitive contacts can be separated by a channel having a unique spacing.

    Abstract translation: 通过将第一电容接触和第二电容接触施加射频(RF)信号给评估结构来提取评估结构的一组参数。 在施加RF信号的同时获取与评价结构的阻抗对应的测量数据,并从测量数据中提取参数组。 在一个实施例中,可以使用多对电容性触点来获取测量数据。 每对电容性触点可以由具有唯一间隔的通道分开。

    Method to increase breakdown voltage of semiconductor devices
    9.
    发明授权
    Method to increase breakdown voltage of semiconductor devices 有权
    提高半导体器件击穿电压的方法

    公开(公告)号:US08318562B2

    公开(公告)日:2012-11-27

    申请号:US12061358

    申请日:2008-04-02

    CPC classification number: H01L29/7787 H01L29/2003 H01L29/66462

    Abstract: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.

    Abstract translation: 一般来说,通过使用高介电强度绝缘包封材料抑制表面闪络来实现半导体器件中的高击穿电压的方法。 在本发明的一个实施例中,通过使用高介电强度绝缘封装材料来抑制AlGaN / GaN异质结构场效应晶体管(HFET)中的表面闪络。 基于III-Nitride的HFET的表面闪络将工作电压限制在远低于GaN击穿电压的水平。

    RADIO-FREQUENCY SWITCH CIRCUIT
    10.
    发明申请
    RADIO-FREQUENCY SWITCH CIRCUIT 有权
    无线电频率开关电路

    公开(公告)号:US20090195232A1

    公开(公告)日:2009-08-06

    申请号:US12364140

    申请日:2009-02-02

    CPC classification number: H03K17/063 H03K2017/066

    Abstract: A switch circuit is provided that includes at least one main switching device and at least one shunt switching device. Each main switching device is connected in series with a conductor that carries an RF signal between an input circuit and an output circuit. Each shunt switching device is connected between a controlling terminal of the main switching device and a high frequency ground. The switch circuit can provide substantially improved OFF state isolation over other approaches.

    Abstract translation: 提供一种开关电路,其包括至少一个主开关装置和至少一个分流开关装置。 每个主开关装置与在输入电路和输出电路之间承载RF信号的导体串联连接。 每个分流开关装置连接在主开关装置的控制端子和高频接地之间。 与其他方法相比,开关电路可以提供显着改进的OFF状态隔离。

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