Low-resistance electrode design
    1.
    发明授权
    Low-resistance electrode design 有权
    低电阻电极设计

    公开(公告)号:US08846473B2

    公开(公告)日:2014-09-30

    申请号:US13458213

    申请日:2012-04-27

    摘要: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    摘要翻译: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    Low-Resistance Electrode Design
    2.
    发明申请
    Low-Resistance Electrode Design 有权
    低电阻电极设计

    公开(公告)号:US20120216161A1

    公开(公告)日:2012-08-23

    申请号:US13458213

    申请日:2012-04-27

    IPC分类号: G06F17/50

    摘要: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    摘要翻译: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR
    3.
    发明申请
    ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR 有权
    增强型绝缘栅结构场效应晶体管

    公开(公告)号:US20080203430A1

    公开(公告)日:2008-08-28

    申请号:US11781338

    申请日:2007-07-23

    IPC分类号: H01L29/778

    摘要: Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

    摘要翻译: 本发明的方面提供了一种在零栅极偏压,低栅极电流和/或高可靠性下具有低功耗的增强模式(E模式)绝缘栅(IG)双异质结构场效应晶体管(DHFET)。 根据本发明的实施例的E型HFET包括:顶部和底部阻挡层; 以及夹在底部和顶部阻挡层之间的沟道层,其中底部和顶部势垒层具有比沟道层更大的带隙,并且其中底部势垒层的极化电荷消耗沟道层和顶部势垒的极化电荷 层在沟道层中诱导载流子; 并且其中底部阻挡层中的总极化电荷大于顶部势垒层中的总极化电荷,使得沟道层在零栅极偏压下基本上耗尽。

    Device and circuit with improved linearity
    4.
    发明授权
    Device and circuit with improved linearity 有权
    器件和电路具有提高的线性度

    公开(公告)号:US08643430B2

    公开(公告)日:2014-02-04

    申请号:US13311633

    申请日:2011-12-06

    IPC分类号: H03B1/00

    CPC分类号: H03H5/12

    摘要: A solution for compensating intermodulation distortion of a component is provided. A circuit element includes multiple connected components. At least two of the connected components comprise current-voltage characteristics of opposite signs (e.g., sublinear and superlinear current-voltage characteristics) such that the current-voltage characteristics of the circuit element produces a level of intermodulation distortion for the circuit element lower than a level of intermodulation distortion for each of the connected components.

    摘要翻译: 提供了用于补偿组件的互调失真的解决方案。 电路元件包括多个连接的部件。 连接的组件中的至少两个包括具有相反符号的电流 - 电压特性(例如,亚线性和超级线性电流 - 电压特性),使得电路元件的电流 - 电压特性产生电路元件的互调失真水平低于 每个连接组件的互调失真水平。

    Composite contact for semiconductor device
    6.
    发明授权
    Composite contact for semiconductor device 有权
    半导体器件的复合接点

    公开(公告)号:US08461631B2

    公开(公告)日:2013-06-11

    申请号:US11781302

    申请日:2007-07-23

    IPC分类号: H01L21/336

    摘要: A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.

    摘要翻译: 提供了一种用于半导体器件的复合触点。 复合触点包括附接到器件中的半导体层的直流导电电极和部分地在直流导电电极上并延伸超过直流导电电极的电容电极。 复合触点提供与半导体层的组合的电阻 - 电容耦合。 结果,当对应的半导体器件以高频率操作时,接触阻抗减小。

    Parameter extraction using radio frequency signals
    7.
    发明授权
    Parameter extraction using radio frequency signals 有权
    使用射频信号进行参数提取

    公开(公告)号:US08395392B2

    公开(公告)日:2013-03-12

    申请号:US12646121

    申请日:2009-12-23

    IPC分类号: G01R31/08 G01R27/00 G01R27/04

    CPC分类号: G01R31/2648

    摘要: A set of parameters of an evaluation structure are extracted by applying a radio frequency (RF) signal through a first capacitive contact and a second capacitive contact to the evaluation structure. Measurement data corresponding to an impedance of the evaluation structure is acquired while the RF signal is applied, and the set of parameters are extracted from the measurement data. In an embodiment, multiple pairs of capacitive contacts can be utilized to acquire measurement data. Each pair of capacitive contacts can be separated by a channel having a unique spacing.

    摘要翻译: 通过将第一电容接触和第二电容接触施加射频(RF)信号给评估结构来提取评估结构的一组参数。 在施加RF信号的同时获取与评价结构的阻抗对应的测量数据,并从测量数据中提取参数组。 在一个实施例中,可以使用多对电容性触点来获取测量数据。 每对电容性触点可以由具有唯一间隔的通道分开。

    Semiconductor device and circuit having multiple voltage controlled capacitors
    8.
    发明授权
    Semiconductor device and circuit having multiple voltage controlled capacitors 有权
    具有多个压控电容器的半导体器件和电路

    公开(公告)号:US07547939B2

    公开(公告)日:2009-06-16

    申请号:US11557744

    申请日:2006-11-08

    IPC分类号: H01L29/94 H01L21/20

    摘要: An improved solution for performing switching, routing, power limiting, and/or the like in a circuit, such as a radio frequency (RF) circuit, is provided. A semiconductor device that includes at least two electrodes, each of which forms a capacitor, such as a voltage-controlled variable capacitor, with a semiconductor channel of the device is used to perform the desired functionality in the RF circuit. The device includes electrodes that can provide high power RF functionality without the use of ohmic contacts or requiring annealing.

    摘要翻译: 提供了一种用于在诸如射频(RF)电路的电路中执行切换,路由,功率限制等的改进的解决方案。 包括至少两个电极的半导体器件被用于在RF电路中执行期望的功能,每个电极形成电容器,例如具有该器件的半导体通道的压控可变电容器。 该器件包括可以在不使用欧姆接触或需要退火的情况下提供高功率RF功能的电极。

    FABRICATION OF SEMICONDUCTOR DEVICE HAVING COMPOSITE CONTACT
    9.
    发明申请
    FABRICATION OF SEMICONDUCTOR DEVICE HAVING COMPOSITE CONTACT 有权
    具有复合接触的半导体器件的制造

    公开(公告)号:US20080206974A1

    公开(公告)日:2008-08-28

    申请号:US11781308

    申请日:2007-07-23

    IPC分类号: H01L21/28

    摘要: A method of fabricating a semiconductor device with a composite contact is provided. The fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure. The composite contact is formed by forming a DC conducting electrode attached to a semiconductor layer in a semiconductor structure and forming a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.

    摘要翻译: 提供了一种制造具有复合触点的半导体器件的方法。 该制造包括在半导体结构中将半导体层形成复合接触。 通过在半导体结构中形成附着到半导体层的直流导电电极形成复合触点,并形成部分在直流导电电极上并延伸超出直流导电电极的电容电极。 复合触点提供与半导体层的组合的电阻 - 电容耦合。 结果,当对应的半导体器件以高频率操作时,接触阻抗减小。

    Profiled contact for semiconductor device
    10.
    发明授权
    Profiled contact for semiconductor device 有权
    半导体器件型材接触

    公开(公告)号:US08552562B2

    公开(公告)日:2013-10-08

    申请号:US12791288

    申请日:2010-06-01

    摘要: A profiled contact for a device, such as a high power semiconductor device is provided. The contact is profiled in both a direction substantially parallel to a surface of a semiconductor structure of the device and a direction substantially perpendicular to the surface of the semiconductor structure. The profiling can limit the peak electric field between two electrodes to approximately the same as the average electrical field between the electrodes, as well as limit the electric field perpendicular to the semiconductor structure both within and outside the semiconductor structure.

    摘要翻译: 提供了诸如大功率半导体器件的器件的成型接触件。 接触件在基本上平行于器件的半导体结构的表面的方向和基本上垂直于半导体结构的表面的方向上成型。 轮廓可以将两个电极之间的峰值电场限制为与电极之间的平均电场大致相同,并且在半导体结构内部和外部限制垂直于半导体结构的电场。