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1.发明授权公开(公告)号：US09514823B2
公开(公告)日：2016-12-06
申请号：US14794741
申请日：2015-07-08
CPC分类号： G11C16/10 , G11C11/5628
摘要： A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.
摘要翻译： 一种方法将第一组连续脉冲应用于一个或多个闪速存储器件中的闪存单元，以使用第一脉冲增量对闪速存储单元进行编程，第一组的每个连续脉冲的电压递增第一脉冲增量。 在接收到施加了第一组连续脉冲之后闪速存储器单元被部分编程的指示之后，基于与闪存单元相关联的编程/擦除循环的数量将第一脉冲增量调整到调整的脉冲增量。 然后使用经调整的脉冲增量将闪存单元的第二组连续脉冲施加，第二组的每个连续脉冲的电压增加经调整的脉冲增量。
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公开(公告)号：US20160233894A1
公开(公告)日：2016-08-11
申请号：US15132143
申请日：2016-04-18
CPC分类号： H03M13/1105 , H03M13/05 , H03M13/1111 , H03M13/1122 , H03M13/1128 , H03M13/114 , H03M13/1162 , H03M13/1171 , H03M13/255 , H03M13/458 , H03M13/615 , H03M13/6505
摘要： Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.
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公开(公告)号：US20150370822A1
公开(公告)日：2015-12-24
申请号：US14841635
申请日：2015-08-31
CPC分类号： G06F17/30132 , G06F3/0626 , G06F3/0643 , G06F3/0673 , G06F12/0864 , G06F12/1018 , G06F17/30371 , G06F17/30949 , G06F2212/6032 , G06F2212/657
摘要： A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.
摘要翻译： 公开了用于将数据存储在散列表中的系统和方法。 该方法包括接收数据，确定数据的位置标识符，其中位置标识符标识哈希表中用于存储数据的位置，并从数据中导出位置标识符，通过提取位置标识符来压缩数据; 以及将所述压缩数据存储在所述散列表的所识别位置。
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公开(公告)号：US20150302930A1
公开(公告)日：2015-10-22
申请号：US14788658
申请日：2015-06-30
发明人： Mark MOSHAYEDI
摘要： A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.
摘要翻译： 闪存存储装置包括具有双层电容器的功率保持电路。 电源为闪存存储设备供电并对双层电容器充电。 当由电源供应的电力被破坏时，双层电容器在闪存存储设备期间的数据传送期间为保持数据的完整性提供电力。 此外，闪存存储装置可以禁止随后的数据传送，直到恢复由电源供应的电力。
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公开(公告)号：US10181355B2
公开(公告)日：2019-01-15
申请号：US14788658
申请日：2015-06-30
发明人： Mark Moshayedi
摘要： A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.
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6.发明申请APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION 审中-公开基于周期信息确定存储器的操作条件的装置和方法公开(公告)号：US20170010836A1
公开(公告)日：2017-01-12
申请号：US15207414
申请日：2016-07-11
CPC分类号： G06F3/0634 , G06F3/0604 , G06F3/0679 , G06F11/0727 , G06F11/076 , G06F11/079 , G11C16/12 , G11C16/14 , G11C16/349 , G11C16/3495
摘要： A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.
摘要翻译： 方法填充用于动态调整非易失性存储器电路的存储器块中的操作条件的参数集。 识别期望的条件限制，并且根据要对存储器块执行的第一存储器操作来计算第一参数。 第一个参数包含在一个参数组中，循环使用内存块，直到操作条件达到所需条件限制为止。 在循环之后，根据对存储器块执行的第二存储器操作来确定第二参数，并且第二参数被包括在参数组中。 可以重复循环，确定和包括第二参数的步骤，直到达到所需数量的循环/参数。 还可以在存储器电路上执行保留烘烤，并且验证由读取操作产生的误码率。
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公开(公告)号：US20160335206A1
公开(公告)日：2016-11-17
申请号：US15156267
申请日：2016-05-16
发明人： Mark MOSHAYEDI , Seyed Jalal SADR
CPC分类号： G06F13/28 , G06F3/0611 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F2212/7202
摘要： A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
摘要翻译： 闪存存储设备基于第一通信协议提供直接存储器访问。 主机选择第一通信协议并向闪存设备提供请求以进行直接存储器访问。 此外，主机向闪存存储设备提供数据块以进行直接存储器访问。 在第一通信协议中，主机不需要为闪存设备提供直接存储器访问的地址。 闪存存储设备将闪存存储设备中的预定地址处的顺序地址存储数据块。 然后，另一主机可以选择第二通信协议，并通过使用第二通信协议来传送闪存中的数据块。
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公开(公告)号：US09411522B2
公开(公告)日：2016-08-09
申请号：US14720697
申请日：2015-05-22
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0688 , G06F11/1441
摘要： A method of transferring data in a flash storage device is provided. A plurality of data segments for transfer between a memory buffer and a plurality of flash memory devices via a plurality of flash memory interfaces is associated with a plurality of respective memory commands. The plurality of memory commands are allocated among the plurality of flash memory interfaces, with each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command. The plurality of data segments are transferred between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, with each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued. The data segments are transferred sequentially in an order corresponding to the queued memory commands.
摘要翻译： 提供了一种在闪速存储设备中传送数据的方法。 用于经由多个闪速存储器接口在存储器缓冲器和多个闪速存储器件之间传送的多个数据段与多个相应的存储器命令相关联。 多个存储器命令被分配在多个闪速存储器接口中，每个相应的存储器命令在相应的存储器接口处排队，以传送与相应存储器命令相关联的相应数据段。 多个数据段基于多个存储器命令在存储器缓冲器和多个闪速存储器件之间传送，每个相应的数据段经由与相应数据段相关联的存储器命令排队的存储器接口传送 。 数据段按照与排队的存储器命令对应的顺序顺序地传送。
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公开(公告)号：US10298261B2
公开(公告)日：2019-05-21
申请号：US15132143
申请日：2016-04-18
摘要： Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.
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公开(公告)号：US10248566B2
公开(公告)日：2019-04-02
申请号：US14722873
申请日：2015-05-27
发明人： Anurag Agarwal , Anand Mitra , Prasad Joshi , Kanishk Rastogi
IPC分类号： G06F9/46 , G06F9/455 , G06F12/0831 , G06F9/50 , G06F12/0888 , G06F12/0842 , G06F9/48 , G06F3/06 , G06F12/06 , G06F12/0871 , G06F12/0866
摘要： Systems and methods for caching data from a plurality of virtual machines may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform.
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