公开(公告)号：US20140008700A1

公开(公告)日：2014-01-09

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

摘要翻译： 描述具有底层扩散阻挡层的锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的栅极电极堆叠。 锗基活性层设置在基板上方，栅电极堆叠下方。 扩散阻挡层设置在基底上方，在锗活性层下方。 接点泄漏抑制层设置在基底上方，在扩散阻挡层下方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的结泄漏抑制层上方。

公开(公告)号：US20210408009A1

公开(公告)日：2021-12-30

申请号：US16913269

申请日：2020-06-26

申请人： Peng ZHENG ,  Varun MISHRA ,  Harold W. KENNEL ,  Eric A. KARL ,  Tahir GHANI

发明人： Peng ZHENG ,  Varun MISHRA ,  Harold W. KENNEL ,  Eric A. KARL ,  Tahir GHANI

IPC分类号： H01L27/11 ,  H01L29/06 ,  H01L29/10

摘要： Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.

公开(公告)号：US09608055B2

公开(公告)日：2017-03-28

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/786 ,  H01L21/28 ,  H01L29/165 ,  H01L29/78 ,  B82Y10/00

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US20160351701A1

公开(公告)日：2016-12-01

申请号：US15117590

申请日：2014-03-27

申请人： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

发明人： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

摘要翻译： 公开了用于将高迁移率应变通道并入翅片式NMOS晶体管（例如，诸如双栅极，触发器等的FinFET）中的技术，其中应力材料被包覆到鳍片的沟道区域上。 在一个示例性实施例中，锗或硅锗膜被包覆在硅散热片上，以便在散热片的芯中提供期望的拉伸应变，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且在典型工艺流程中的多个位置处可以发生熔覆沉积。 在各种实施例中，可以以最小宽度（或稍后变薄）形成翅片，以便提高晶体管性能。 在一些实施例中，变薄的翅片也增加穿过包覆翅片的芯的拉伸应变。 在一些情况下，通过添加嵌入式硅外延源和漏极可以进一步增强芯中的应变。

公开(公告)号：US20160240616A1

公开(公告)日：2016-08-18

申请号：US15024348

申请日：2013-12-16

申请人： Stephen M. CEA ,  Roza KOTLYAR ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Kelin J. KUHN ,  Tahir GHANI

发明人： Stephen M. CEA ,  Roza KOTLYAR ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Kelin J. KUHN ,  Tahir GHANI

IPC分类号： H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092 ,  H01L29/04 ,  H01L29/161

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66818 ,  H01L29/7781 ,  H01L29/7782

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor.

摘要翻译： 与没有松弛衬底的应变NMOS和PMOS器件有关的技术和方法，以及这样的半导体器件的系统及其方法。

公开(公告)号：US09240322B2

公开(公告)日：2016-01-19

申请号：US13995171

申请日：2011-12-09

申请人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

发明人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

IPC分类号： H01L21/425 ,  H01L21/268 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/2686 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/78

摘要： A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

摘要翻译： 脉冲激光退火技术包括执行半导体晶片的选定区域的注入。 执行所选择的区域的共同组成植入物，并且执行所选区域的脉冲激光退火。 还可以进行所选择的区域的非失配植入物。 在一个实施例中，所选择的区域的植入被实施为本体植入物。 在另一个实施例中，辅助植入物作为原位非供体植入物进行。 在另一个实施例中，所选择的区域的植入物和共同构成植入物作为原位供体和共同构成植入物进行。

公开(公告)号：US20160276347A1

公开(公告)日：2016-09-22

申请号：US15024347

申请日：2013-12-16

申请人： Stephen M. CEA ,  Roza KOTLYAR ,  Harold W. KENNEL ,  Kelin J. KUHN ,  Tahir GHANI

发明人： STEPHEN M CEA ,  ROZA KOTLYAR ,  HAROLD W KENNEL ,  KELIN J KUHN ,  TAHIR GHANI

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.

摘要翻译： 与用于半导体器件的双应变包覆层有关的技术和方法以及包含这种半导体器件的系统。

公开(公告)号：US20130154016A1

公开(公告)日：2013-06-20

申请号：US13685369

申请日：2012-11-26

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Harold W. Kennel

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Harold W. Kennel

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/267 ,  H01L21/28525 ,  H01L21/28568 ,  H01L29/165 ,  H01L29/207 ,  H01L29/42392 ,  H01L29/452 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78696

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用诸如硅或硅锗（SiGe）源极/漏极区域上的一种或多种金属/合金的金属接触来实现。 根据一个示例性实施例，在源极/漏极和接触金属之间设置中间锡掺杂的III-V材料层，以显着降低接触电阻。 可以使用锡掺杂层的部分或完全氧化来进一步提高接触电阻。 在一些示例情况下，锡掺杂的III-V材料层在衬底附近具有半导体相和金属接触附近的氧化物相。 根据本公开，许多晶体管配置和合适的制造工艺将是显而易见的，包括平面和非平面晶体管结构（例如，FinFET，纳米线晶体管等），以及应变和未染色的通道结构。

公开(公告)号：US20130267084A1

公开(公告)日：2013-10-10

申请号：US13995171

申请日：2011-12-09

申请人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

发明人： Jacob M. Jensen ,  Harold W. Kennel ,  Tahir Ghani ,  Robert D. James ,  Mark Y. Liu

IPC分类号： H01L21/268

CPC分类号： H01L21/2686 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/78

摘要： A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.

摘要翻译： 脉冲激光退火技术包括执行半导体晶片的选定区域的注入。 执行所选择的区域的共同组成植入物，并且执行所选区域的脉冲激光退火。 还可以进行所选择的区域的非失配植入物。 在一个实施例中，所选择的区域的植入被实施为本体植入物。 在另一个实施例中，辅助植入物作为原位非供体植入物进行。 在另一个实施例中，所选择的区域的植入物和共同构成植入物作为原位供体和共同构成植入物进行。

公开(公告)号：US09397166B2

公开(公告)日：2016-07-19

申请号：US13977394

申请日：2011-12-20

申请人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

发明人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

摘要： Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

摘要翻译： 本发明的实施例提供具有应变通道区域的晶体管结构。 通过源极和漏极区域中相对于晶体管的沟道区域的晶格失配产生应变。 在本发明的实施例中，晶体管沟道区由锗，硅，锗和硅的组合，或锗，硅和锡的组合组成，源极和漏极区由掺杂的III-V族化合物半导体 材料。 本发明的实施例可用于各种晶体管结构，例如具有由纳米线或纳米带构成的沟道区的触发，大电流和单栅极晶体管和晶体管。