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    Local power gate (LPG) interfaces for power-aware operations
    5.
    发明授权
    Local power gate (LPG) interfaces for power-aware operations 有权
    用于电源感知操作的本地电源门（LPG）接口

    公开(公告)号：US09519324B2

    公开(公告)日：2016-12-13

    申请号：US14225612

    申请日：2014-03-26

    申请人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

    发明人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

    IPC分类号： G06F1/32 ,  G06F9/22

    CPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

    摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

    摘要翻译： 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。 主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。 主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地 并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

    Recoverable parity and residue error
    6.
    发明授权
    Recoverable parity and residue error 有权
    可恢复奇偶校验和残差误差

    公开(公告)号：US08909988B2

    公开(公告)日：2014-12-09

    申请号：US13436319

    申请日：2012-03-30

    申请人： Zeev Sperber ,  Ofer Levy ,  Michael Mishaeli ,  Ron Gabor

    发明人： Zeev Sperber ,  Ofer Levy ,  Michael Mishaeli ,  Ron Gabor

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1405 ,  G06F11/1032

    摘要： An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.

    摘要翻译： 错误恢复单元，其可以包括用于检测调度端口中的错误的错误逻辑和被配置为生成错误的时间戳的时间戳逻辑。 错误恢复单元还可以包括检查逻辑，以基于时间戳来确定与错误相关联的指令是否已经退休。 如果指令已经停止，则可能启动机器检查错误逻辑。 如果指令还没有退出，则可以启动纠错逻辑来恢复错误并重新执行指令。 因此，可以恢复投机错误，而不需要调用机器检查错误，这是因为其灾难性质而不期望的。 因此，机器检查错误可能会显着降低。

    CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION
    7.
    发明申请
    CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION 有权
    条件记忆障碍协助抑制

    公开(公告)号：US20150261590A1

    公开(公告)日：2015-09-17

    申请号：US14214910

    申请日：2014-03-15

    申请人： Zeev Sperber ,  Robert Valentine ,  Offer Levy ,  Michael Mishaeli ,  Gal Ofir

    发明人： Zeev Sperber ,  Robert Valentine ,  Offer Levy ,  Michael Mishaeli ,  Gal Ofir

    IPC分类号： G06F11/07

    CPC分类号： G06F11/079 ,  G06F11/0721 ,  G06F11/073

    摘要： In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.

    摘要翻译： 在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障， 更多的故障抑制位。

    Extension of CPU context-state management for micro-architecture state
    8.
    发明授权
    Extension of CPU context-state management for micro-architecture state 有权
    扩展用于微架构状态的CPU上下文状态管理

    公开(公告)号：US09361101B2

    公开(公告)日：2016-06-07

    申请号：US13538252

    申请日：2012-06-29

    申请人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    发明人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

    摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

    摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。