公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/10

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20140223226A1

公开(公告)日：2014-08-07

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/14

CPC分类号： G06F11/1405 ,  G06F11/1064

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

摘要翻译： 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：US09626333B2

公开(公告)日：2017-04-18

申请号：US13977727

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

发明人： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

IPC分类号： G06F9/00 ,  G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

公开(公告)号：US08914617B2

公开(公告)日：2014-12-16

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F9/34 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US08972697B2

公开(公告)日：2015-03-03

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/02

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

公开(公告)号：US20130326160A1

公开(公告)日：2013-12-05

申请号：US13487184

申请日：2012-06-02

申请人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

发明人： Zeev Sperber ,  Robert Valentine ,  Guv Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/00

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。 有限状态机有助于收集操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 如果mask元素具有第一个值，则访问地址以加载相应的数据元素。 根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。 响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

公开(公告)号：US20110208918A1

公开(公告)日：2011-08-25

申请号：US12978513

申请日：2010-12-24

申请人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

发明人： Shlomo Raikin ,  David J. Sager ,  Zeev Sperber ,  Evgeni Krimer ,  Ori Lempel ,  Stanislav Shwartsman ,  Adi Yoaz ,  Omer Golz

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/384 ,  Y02D10/13

摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

摘要翻译： 描述与硬件移动消除和/或下一页预取相关的方法和装置。 在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。 在一个实施例中，公开了下一页预取器。 还描述和要求保护其他实施例。

公开(公告)号：US09519324B2

公开(公告)日：2016-12-13

申请号：US14225612

申请日：2014-03-26

申请人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

发明人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

IPC分类号： G06F1/32 ,  G06F9/22

CPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

摘要翻译： 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。 主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。 主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地 并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

公开(公告)号：US07882325B2

公开(公告)日：2011-02-01

申请号：US11963295

申请日：2007-12-21

申请人： Zeev Sperber ,  Robert Valentine ,  Ehud Cohen ,  Doron Orenstien ,  Benny Eitan

发明人： Zeev Sperber ,  Robert Valentine ,  Ehud Cohen ,  Doron Orenstien ,  Benny Eitan

IPC分类号： G06F12/04

CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3887

摘要： A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.

摘要翻译： 提供执行N位或2N位负载的单个微指令。 具有N位负载端口的微处理器在单个周期中执行N位负载或2N位负载，同时使用相同的微指令用于N位和2N位负载。

公开(公告)号：US06944720B2

公开(公告)日：2005-09-13

申请号：US10402827

申请日：2003-03-27

申请人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

发明人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0875 ,  G06F12/1054 ,  G06F2212/401

摘要： A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

摘要翻译： 提供了一种用于存储多种数据类型的存储器系统。 存储器系统包括主存储器，本地高速缓存和翻译单元。 本地缓存具有多个条目，每个条目包括用于存储数据的数据字段和用于指示所存储的数据的存储状态的状态字段。 翻译单元包括翻译后备缓冲器（TLB）和状态缓存（STC）。 TLB存储主存储器中的数据的地址转换，并且STC存储由地址转换指示的数据的存储状态。