公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/10

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20140223226A1

公开(公告)日：2014-08-07

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/14

CPC分类号： G06F11/1405 ,  G06F11/1064

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

摘要翻译： 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：US09448879B2

公开(公告)日：2016-09-20

申请号：US13994105

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

发明人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07

CPC分类号： G06F11/1064 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1407

摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

摘要翻译： 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

公开(公告)号：US09405646B2

公开(公告)日：2016-08-02

申请号：US13992506

申请日：2011-09-29

申请人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

发明人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC分类号： G06F11/00 ,  G06F11/263 ,  G06F11/36

CPC分类号： G06F11/263 ,  G06F11/3664 ,  G06F11/3688

摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

摘要翻译： 公开了一种向存储器注入错误的装置和方法。 在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。 如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

公开(公告)号：US08645797B2

公开(公告)日：2014-02-04

申请号：US13323405

申请日：2011-12-12

申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G11C29/00

CPC分类号： G06F11/2236

摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。

公开(公告)号：US20130339829A1

公开(公告)日：2013-12-19

申请号：US13995458

申请日：2011-12-29

申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

IPC分类号： G06F11/10

CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：US09317360B2

公开(公告)日：2016-04-19

申请号：US13995458

申请日：2011-12-29

申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F11/10 ,  G06F11/07

CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：US09342394B2

公开(公告)日：2016-05-17

申请号：US13997301

申请日：2011-12-29

申请人： Murugasamy Nachimuthu ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Jose A. Vargas ,  Rajender Kuramkote

发明人： Murugasamy Nachimuthu ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Jose A. Vargas ,  Rajender Kuramkote

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/36 ,  G06F21/57

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/3664 ,  G06F21/57

摘要： Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

摘要翻译： 本文描述了各种实施例。 一些实施例包括操作系统和平台。 该平台包括具有错误寄存器的处理器。 操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。 描述和要求保护其他实施例。

公开(公告)号：US20130275810A1

公开(公告)日：2013-10-17

申请号：US13992506

申请日：2011-09-29

申请人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

发明人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC分类号： G06F11/263

CPC分类号： G06F11/263 ,  G06F11/3664 ,  G06F11/3688

摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

摘要翻译： 公开了一种向存储器注入错误的装置和方法。 在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。 如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

公开(公告)号：US20130151930A1

公开(公告)日：2013-06-13

申请号：US13323405

申请日：2011-12-12

申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G06F11/10

CPC分类号： G06F11/2236

摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。