公开(公告)号：US20060018557A1

公开(公告)日：2006-01-26

申请号：US11188261

申请日：2005-07-22

申请人： Hyeok-Man Kwon ,  Jae-Hong Park ,  Tae-Sun Kim

发明人： Hyeok-Man Kwon ,  Jae-Hong Park ,  Tae-Sun Kim

IPC分类号： G06K9/36

CPC分类号： H04N19/117 ,  H04N19/136 ,  H04N19/16 ,  H04N19/176

摘要： Provided is an apparatus and method for filtering a blocking effect in an image, which removes the blocking effect that may occur in an image that is compressed in block units in compression and/or decompression of a moving image. The apparatus and method for filtering a blocking effect in an image involves a single blocky pattern and a double blocky pattern and uses filtering that is suitable for these patterns. Also, the method for filtering a blocking effect in an image separately filters pixels in a top field and pixels in a bottom field when a macroblock in a frame picture is coded in a field mode.

摘要翻译： 提供一种用于对图像中的阻挡效果进行滤波的装置和方法，该装置和方法消除了在运动图像的压缩和/或解压缩中以块为单位压缩的图像中可能发生的阻塞效果。 用于过滤图像中的阻塞效应的装置和方法涉及单个块状图案和双块图案，并且使用适合于这些图案的滤波。 此外，当帧场图像中的宏块以场模式被编码时，用于滤除图像中的块效应的方法分别过滤顶场中的像素和底场中的像素。

公开(公告)号：US06714466B2

公开(公告)日：2004-03-30

申请号：US10080710

申请日：2002-02-25

申请人： Sang Wook Park ,  Joo Hyung Mun ,  Hyeok Man Kwon

发明人： Sang Wook Park ,  Joo Hyung Mun ,  Hyeok Man Kwon

IPC分类号： G11C700

CPC分类号： G11C29/72 ,  G11C29/44

摘要： Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing the fail address data. Accordingly, the test and repair analysis operations are simultaneously performed. The capability of the rearrangement that includes the movement and exchange between the column and row fail address data enhances redundancy efficiency and yields of the memory device.

摘要翻译： 采用两个临时缓冲器，其中存储从测试操作指定的故障地址数据，其中一个临时缓冲器将故障地址数据传送到数据缓冲器，以执行修复分析，而另一个存储故障地址数据 。 因此，同时执行测试和修复分析操作。 包括列和行失败地址数据之间的移动和交换的重新布置的能力提高了存储器件的冗余效率和产量。

公开(公告)号：US20150200154A1

公开(公告)日：2015-07-16

申请号：US14597183

申请日：2015-01-14

申请人： Yun-seok CHOI ,  Hyeok-man KWON ,  Cha-jea JO ,  Tae-je CHO

发明人： Yun-seok CHOI ,  Hyeok-man KWON ,  Cha-jea JO ,  Tae-je CHO

IPC分类号： H01L23/48 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/074 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

摘要翻译： 提供了一种堆叠的半导体封装，其由于堆叠在下芯片上的上半导体芯片的特性而使对下半导体芯片的设计的限制最小化。 堆叠半导体封装包括具有贯穿电极区域的下部芯片，其中设置有多个贯通电极; 以及堆叠在下芯片上并具有焊盘区域的至少一个上芯片，其中设置有与多个贯通电极对应的多个焊盘。 焊盘区域沿着等分上部芯片的有效表面的中心轴线设置。 上芯片的焊盘区域的中心轴被配置在从下芯片的有源面的长度方向的中心轴偏移的位置。

公开(公告)号：US09543231B2

公开(公告)日：2017-01-10

申请号：US14597183

申请日：2015-01-14

申请人： Yun-seok Choi ,  Hyeok-man Kwon ,  Cha-jea Jo ,  Tae-je Cho

发明人： Yun-seok Choi ,  Hyeok-man Kwon ,  Cha-jea Jo ,  Tae-je Cho

IPC分类号： H01L25/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/074 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

摘要翻译： 提供了一种堆叠的半导体封装，其由于堆叠在下芯片上的上半导体芯片的特性而使对下半导体芯片的设计的限制最小化。 堆叠半导体封装包括具有贯穿电极区域的下部芯片，其中设置有多个贯通电极; 以及堆叠在下芯片上并具有焊盘区域的至少一个上芯片，其中设置有与多个贯通电极对应的多个焊盘。 焊盘区域沿着等分上部芯片的有效表面的中心轴线设置。 上芯片的焊盘区域的中心轴被配置在从下芯片的有源面的长度方向的中心轴偏移的位置。

公开(公告)号：US20160110253A1

公开(公告)日：2016-04-21

申请号：US14978538

申请日：2015-12-22

申请人： Sun-gyeum Kim ,  Hyeok-man Kwon ,  Young-jun Kwon ,  Ki-young Choi ,  Jun-whan Ahn

发明人： Sun-gyeum Kim ,  Hyeok-man Kwon ,  Young-jun Kwon ,  Ki-young Choi ,  Jun-whan Ahn

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F11/1064 ,  G11C11/1653 ,  G11C11/1677 ,  G11C29/52

摘要： In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

摘要翻译： 在一个实施例中，存储器件包括数据存储区域和纠错（ECC）区域。 数据存储区域被配置为存储第一数量的数据块。 ECC区域被配置为存储第二数量的ECC块。 第二数量的ECC块中的每一个被配置为存储ECC信息。 ECC块的第二数量与第一数量块相关联，第二数量小于第一数量。