公开(公告)号：US20150200154A1

公开(公告)日：2015-07-16

申请号：US14597183

申请日：2015-01-14

申请人： Yun-seok CHOI ,  Hyeok-man KWON ,  Cha-jea JO ,  Tae-je CHO

发明人： Yun-seok CHOI ,  Hyeok-man KWON ,  Cha-jea JO ,  Tae-je CHO

IPC分类号： H01L23/48 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/074 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

摘要： Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

摘要翻译： 提供了一种堆叠的半导体封装，其由于堆叠在下芯片上的上半导体芯片的特性而使对下半导体芯片的设计的限制最小化。 堆叠半导体封装包括具有贯穿电极区域的下部芯片，其中设置有多个贯通电极; 以及堆叠在下芯片上并具有焊盘区域的至少一个上芯片，其中设置有与多个贯通电极对应的多个焊盘。 焊盘区域沿着等分上部芯片的有效表面的中心轴线设置。 上芯片的焊盘区域的中心轴被配置在从下芯片的有源面的长度方向的中心轴偏移的位置。

公开(公告)号：US08723315B2

公开(公告)日：2014-05-13

申请号：US13470572

申请日：2012-05-14

申请人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

发明人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

摘要： A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

摘要翻译： 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US20120223427A1

公开(公告)日：2012-09-06

申请号：US13470572

申请日：2012-05-14

申请人： Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

发明人： Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

IPC分类号： H01L23/485

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

摘要： A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

摘要翻译： 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US07638365B2

公开(公告)日：2009-12-29

申请号：US11623279

申请日：2007-01-15

申请人： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

发明人： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L27/146 ,  H01L27/148 ,  H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

摘要翻译： 提供一种堆叠式芯片封装及其形成方法。 间隔件形成在上芯片的一侧。 在间隔件上形成导线以电连接上芯片和下芯片。 堆叠式芯片封装的可靠性得到改善，因为引线接合不用于电连接上下芯片。 此外，堆叠的芯片封装的整体尺寸可以减小，因为接合线环的高度对整个堆叠的芯片封装高度没有贡献。

公开(公告)号：US20090278561A1

公开(公告)日：2009-11-12

申请号：US12330146

申请日：2008-12-08

申请人： Cha-jea Jo ,  Tae-gyeong Chung ,  Hoon-jung Kim ,  Nam-seog Kim ,  Chang-seong Jeon

发明人： Cha-jea Jo ,  Tae-gyeong Chung ,  Hoon-jung Kim ,  Nam-seog Kim ,  Chang-seong Jeon

IPC分类号： G01R1/073

CPC分类号： G01R31/2889 ,  G01R1/06716 ,  G01R1/06733

摘要： The probe card is comprised of a probe card wafer, a plurality of through via electrodes penetrating the probe card wafer; and a plurality of redistributed wiring probe needle structures, each being connected to the through via electrodes protruding from a surface of the probe card wafer.

摘要翻译： 探针卡由探针卡晶片，穿过探针卡晶片的多个通孔电极组成; 以及多个重新分布的布线探针针结构，每个连接到从探针卡晶片的表面突出的通孔电极。

公开(公告)号：US20080157287A1

公开(公告)日：2008-07-03

申请号：US12003798

申请日：2008-01-02

申请人： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

发明人： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

摘要翻译： 提供半导体器件及其形成方法。 所述方法可以包括在初步半导体衬底中形成孔，在初步半导体衬底的孔中形成绝缘层，在绝缘层和初级半导体衬底上形成电镀导电层，形成与电镀导电性接触的晶种金属层 层，并且生长种子金属层以形成穿硅通孔（TSV）。 TSV可以通过电镀工艺形成，使得种子金属层从孔的下部生长到孔的上部。

公开(公告)号：US20080141933A1

公开(公告)日：2008-06-19

申请号：US11984402

申请日：2007-11-16

申请人： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

发明人： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

IPC分类号： B05C5/00

CPC分类号： C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885

摘要： Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.

摘要翻译： 提供了一种用于对具有期望层的半导体物体进行电镀的半导体电镀系统。 半导体电镀系统包括：电镀槽，其配置为容纳用于电镀半导体物体的电镀液;以及电镀液感应装置，其被配置为使电镀液向半导体物体螺旋状流动。

公开(公告)号：US08088648B2

公开(公告)日：2012-01-03

申请号：US12840656

申请日：2010-07-21

申请人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L21/50 ,  H01L21/60

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

摘要翻译： 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20080157332A1

公开(公告)日：2008-07-03

申请号：US12000384

申请日：2007-12-12

申请人： Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L23/538 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/48463 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107

摘要： A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package. A method of manufacturing a stacked semiconductor package may include: forming semiconductor packages; stacking the semiconductor packages on a substrate; forming a mask pattern on the semiconductor packages and the substrate to expose the edges of the semiconductor packages; performing an electroless plating process on the edges of the semiconductor packages to form a seed layer; and performing an electroplating process on the seed layer to form an interconnection member for electrically connecting the conductive lines to each other.

摘要翻译： 层叠的半导体封装可以包括：衬底; 堆叠在基板上的半导体封装; 形成在所述半导体封装的边缘上的互连构件; 以及形成在所述互连构件上的导电加强构件。 每个半导体封装可以包括导线。 互连构件可将半导体封装的导线电连接至至少一个其它半导体封装的导线。 层叠半导体封装的制造方法可以包括：形成半导体封装; 将半导体封装堆叠在衬底上; 在所述半导体封装和所述衬底上形成掩模图案以暴露所述半导体封装的边缘; 在半导体封装的边缘上进行化学镀处理以形成种子层; 以及在种子层上进行电镀处理以形成用于将导线彼此电连接的互连构件。

公开(公告)号：US20150162265A1

公开(公告)日：2015-06-11

申请号：US14450723

申请日：2014-08-04

申请人： Cha-Jea JO ,  Tae-Je CHO

发明人： Cha-Jea JO ,  Tae-Je CHO

IPC分类号： H01L23/48

CPC分类号： H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/00

摘要： Semiconductor packages including chips having through silicon vias (TSVs) and methods of manufacturing the same may be provided to provide reliable and thinner semiconductor packages by mitigating or preventing a crack from occurring at an uppermost chip. The semiconductor package including a substrate, a first chip stacked on the substrate, the first chip including a plurality of through silicon vias (TSVs), an uppermost chip stacked on the first chip, the uppermost chip being thicker than the first chip, a first gap fill portion covering at least a portion of a side surface of the uppermost chip while filling a space between the first chip and the uppermost chip, and a sealant for sealing the first chip, the uppermost chip, and the first gap fill portion may be provided.

摘要翻译： 可以提供包括通过硅通孔（TSV）的芯片的半导体封装及其制造方法，以通过减轻或防止在最高芯片处发生裂纹来提供可靠和更薄的半导体封装。 所述半导体封装包括衬底，堆叠在所述衬底上的第一芯片，所述第一芯片包括多个穿通硅通孔（TSV），堆叠在所述第一芯片上的最上面的芯片，所述最上面的芯片比所述第一芯片厚;第一芯片， 间隙填充部分，当填充第一芯片和最上面的芯片之间的空间时，覆盖最上面的芯片的侧表面的至少一部分，并且用于密封第一芯片，最上面的芯片和第一间隙填充部分的密封剂可以是 提供。