公开(公告)号：US07525339B2

公开(公告)日：2009-04-28

申请号：US11717959

申请日：2007-03-14

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: H03K17/16

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Abstract translation: 用于在数据读取模式期间测试ODT电路是开启还是关闭的半导体存储器件包括管芯端接（ODT）电路和ODT状态信息输出单元。 ODT电路包括至少一个ODT电阻。 ODT状态信息输出单元响应于当从存储器单元输出数据时在数据读取模式期间的ODT控制信号，输出指示ODT电路是开或关的ODT状态信息信号。 利用在数据读取模式期间能够测试ODT电阻是开或关的半导体存储器件和方法，可以在数据读取期间测试ODT电路是开或关。

公开(公告)号：US20080205174A1

公开(公告)日：2008-08-28

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US07426153B2

公开(公告)日：2008-09-16

申请号：US11481187

申请日：2006-07-06

Applicant: Hyong-Yong Lee

Inventor： Hyong-Yong Lee

IPC: G11C8/18

CPC classification number: G11C7/1045 ,  G11C7/1066 ,  G11C29/46

Abstract: Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level. Therefore, it is possible to solve the problem of restrictions regarding the operating frequency of the mode register of the semiconductor device by performing a test mode register setting operation independent of a clock signal applied to the semiconductor device.

Abstract translation: 提供了用于半导体器件的模式寄存器设置方法和装置，以便抑制半导体器件的模式寄存器在半导体器件执行典型的写入或读取操作之前发生的模式寄存器的频率的限制，作为其中 半导体器件工作增加。 模式寄存器设置方法和装置可以应用于例如DDR型半导体器件。 如果芯片选择信号/ CS至少保持第一时间的逻辑低电平，则半导体器件可以启动时钟无关模式寄存器设置操作。 在时钟独立模式寄存器设置操作中，当施加到半导体器件的数据选通信号的逻辑电平从逻辑低电平转换到逻辑高电平时，可以采样模式寄存器组（MRS）命令和MRS码位 水平。 因此，可以通过执行独立于施加到半导体器件的时钟信号的测试模式寄存器设置操作来解决关于半导体器件的模式寄存器的工作频率的限制的问题。

公开(公告)号：US20070222476A1

公开(公告)日：2007-09-27

申请号：US11717959

申请日：2007-03-14

Applicant: Hyong-Yong Lee

Inventor： Hyong-Yong Lee

IPC: H03K19/003

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Abstract translation: 用于在数据读取模式期间测试ODT电路是开启还是关闭的半导体存储器件包括管芯端接（ODT）电路和ODT状态信息输出单元。 ODT电路包括至少一个ODT电阻。 ODT状态信息输出单元响应于当从存储器单元输出数据时在数据读取模式期间的ODT控制信号，输出指示ODT电路是开或关的ODT状态信息信号。 利用在数据读取模式期间能够测试ODT电阻是开或关的半导体存储器件和方法，可以在数据读取期间测试ODT电路是开或关。

公开(公告)号：US08243540B2

公开(公告)日：2012-08-14

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

公开(公告)号：US20120014189A1

公开(公告)日：2012-01-19

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US08036052B2

公开(公告)日：2011-10-11

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US20100169518A1

公开(公告)日：2010-07-01

申请号：US12654749

申请日：2009-12-30

Applicant: Hyong-Yong Lee ,  Bu-Jin Kim

Inventor： Hyong-Yong Lee ,  Bu-Jin Kim

IPC: G06F5/14

CPC classification number: G06F5/16

Abstract: A semiconductor memory device includes a plurality of output buffer units connected to a plurality of terminals. Each of the output buffer units includes a first high speed data output (HSDO) buffer adapted to buffer even-numbered data of a corresponding data row among a plurality of data rows and to output the even-numbered data to a corresponding terminal among the plurality of terminals, a second HSDO buffer adapted to buffer odd-numbered data of the corresponding data row and to output the odd-numbered data to the corresponding terminal, and a buffer selector adapted to select and activate the first HSDO buffer and/or the second HSDO buffer in response to a corresponding control signal out of at least one control signal during a HSDO test.

Abstract translation: 半导体存储器件包括连接到多个端子的多个输出缓冲单元。 每个输出缓冲器单元包括第一高速数据输出（HSDO）缓冲器，用于缓冲多个数据行中对应的数据行的偶数数据，并将偶数数据输出到多个数据行中的对应的终端 的第二HSDO缓冲器，适于缓冲相应数据行的奇数数据并将奇数数据输出到对应终端;以及缓冲器选择器，适于选择并激活第一HSDO缓冲器和/或第二HSDO缓冲器 HSDO缓冲器响应于在HSDO测试期间的至少一个控制信号中的相应控制信号。

公开(公告)号：US20080225608A1

公开(公告)日：2008-09-18

申请号：US12049160

申请日：2008-03-14

Applicant: Chung-Ki LEE ,  Hyong-Yong LEE

Inventor： Chung-Ki LEE ,  Hyong-Yong LEE

IPC: G11C7/00

CPC classification number: G11C7/24 ,  G11C5/143 ,  G11C7/22 ,  G11C29/02 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate a control signal corresponding to the range of the level of the external power voltage responsive to the voltage detecting signal. As a result, the semiconductor memory device can perform an operation for satisfying an access time characteristic according to a specification responsive to the control signal.

Abstract translation: 半导体存储器件及其控制信号产生方法。 半导体存储器件可以包括电压范围检测器，其被配置为产生对应于外部电源电压的电平的范围的电压检测信号。 可以使用控制信号产生部分来响应于电压检测信号产生对应于外部电源电压的电平的范围的控制信号。 结果，半导体存储器件可以根据控制信号执行根据规格满足访问时间特性的操作。

公开(公告)号：US20080031055A1

公开(公告)日：2008-02-07

申请号：US11803454

申请日：2007-05-15

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: G11C29/00 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.

Abstract translation: 半导体存储器件及其测试方法即使在输入高频外部时钟信号时也能执行低频测试操作。 用于测试半导体存储器件的方法包括：当包括在控制命令中的MRS命令指定写入和读取测试操作时，解释来自多个外部控制信号的控制命令并产生低频操作控制信号; 当写命令被输入作为控制命令时，响应于低频操作控制信号将写入命令转换成低频写入命令，响应于低频操作控制产生内部低频时钟信号 信号，并且基于内部低频时钟信号执行低频写入操作; 并且缓冲外部时钟信号以产生内部正常频率时钟信号，并且当输入读取命令作为控制命令时，响应于读取命令，基于内部正常频率时钟信号执行读取操作。