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23 条记录 (耗时 0.021 秒)

    Integrated circuit with a reprogrammable nonvolatile switch for selectively connecting a source for a signal to a circuit
    1.
    发明授权
    Integrated circuit with a reprogrammable nonvolatile switch for selectively connecting a source for a signal to a circuit 有权
    具有可再编程非易失性开关的集成电路，用于选择性地将信号源连接到电路

    公开(公告)号：US06756632B1

    公开(公告)日：2004-06-29

    申请号：US10641609

    申请日：2003-08-15

    申请人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

    发明人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

    IPC分类号： H01L29788

    CPC分类号： H03K19/17748 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/7885 ,  H03K19/1778

    摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

    摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有位于通道的第一部分上方的浮动栅极的分离栅极型，以及位于通道的第二部分上方的控制栅极，其中电子通过热电子注入机制注入浮置栅极。 非易失性存储单元被来自浮动栅极的电子的作用擦除，通过Fowler-Nordheim隧穿隧道穿过与第二区域相邻的控制栅极。 因此，在编程或擦除期间，不会对第二区域施加高电压。 因此，具有第二区域的非易失性存储单元可以直接连接到MOS晶体管的栅极，其一起形成非易失性可编程开关。

    Word line voltage boosting circuit and a memory array incorporating same
    2.
    发明授权
    Word line voltage boosting circuit and a memory array incorporating same 有权

    公开(公告)号：US07403418B2

    公开(公告)日：2008-07-22

    申请号：US11241582

    申请日：2005-09-30

    申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

    发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C16/08

    摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

    Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing
    3.
    发明授权
    Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing 有权
    在沟槽中具有电荷捕获层的这种双向非易失性存储单元和这种存储单元阵列，以及制造方法

    公开(公告)号：US07470949B1

    公开(公告)日：2008-12-30

    申请号：US11828213

    申请日：2007-07-25

    申请人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

    发明人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

    IPC分类号： H01L27/108

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

    摘要： A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

    摘要翻译： 非易失性存储单元具有用于在其上存储电荷的电荷捕获层。 电池是第一导电性衬底中的双向电池。 电池具有两个间隔开的沟槽。 在每个沟槽内，其底部是第二导电性的区域。 一个通道从一个沟槽底部的一个区域沿着该沟槽的侧壁延伸到衬底的顶部平坦表面，并且沿相邻沟槽的侧壁延伸到相邻沟槽底部的区域 。 捕获层沿着两个沟槽中的每一个的侧壁。 控制栅极位于每个沟槽中，每个沟槽沿着侧壁电容耦合到捕获层，并且在沟槽的底部与区域电容耦合。 每个沟槽可以存储多个位。

    Data encoder and decoder using memory-specific parity-check matrix
    6.
    发明授权
    Data encoder and decoder using memory-specific parity-check matrix 有权
    数据编码器和解码器使用特定于存储器的奇偶校验矩阵

    公开(公告)号：US08954822B2

    公开(公告)日：2015-02-10

    申请号：US13679970

    申请日：2012-11-16

    申请人： Jack Edward Frayer ,  Aaron K. Olbrich

    发明人： Jack Edward Frayer ,  Aaron K. Olbrich

    IPC分类号： G11C29/00 ,  H03M13/13 ,  G06F11/10

    CPC分类号： H03M13/13 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2948 ,  H03M13/356

    摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.

    摘要翻译： 错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。 该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。 该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联 存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。

    INTELLIGENT BIT RECOVERY FOR FLASH MEMORY
    7.
    发明申请
    INTELLIGENT BIT RECOVERY FOR FLASH MEMORY 有权
    用于闪存存储器的智能位恢复

    公开(公告)号：US20120324276A1

    公开(公告)日：2012-12-20

    申请号：US13285873

    申请日：2011-10-31

    申请人： Jack Edward Frayer ,  Aaron Keith Olbrich ,  Paul Roger Stonelake ,  Anand Krishnamurthi Kulkarni ,  Yale Yueh Ma

    发明人： Jack Edward Frayer ,  Aaron Keith Olbrich ,  Paul Roger Stonelake ,  Anand Krishnamurthi Kulkarni ,  Yale Yueh Ma

    IPC分类号： G06F11/16

    CPC分类号： G11C16/3427 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422

    摘要： A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

    摘要翻译： 提供了一种方法和系统智能位恢复。 智能位恢复确定哪些位正在切换，并且检查潜在位模式的子集以确定潜在位模式的子集中哪一个是有效的。 该子集是潜在位模式的一小部分，并且基于对闪存的理解以及可能导致切换位的问题。 智能位恢复可以分析闪速存储器的至少一个方面以识别哪个问题潜在地导致切换位，并且选择潜在位模式的子集作为所确定问题的解决方案。 或者，智能位恢复为潜在的潜在问题选择潜在的位模式。 以任一方式，通过智能位恢复检查的潜在位模式的子集是整个潜在位模式集合的一小部分。

    High bandwidth distributed computing solid state memory storage system
    8.
    发明申请
    High bandwidth distributed computing solid state memory storage system 审中-公开
    高带宽分布式计算固态存储系统

    公开(公告)号：US20080114924A1

    公开(公告)日：2008-05-15

    申请号：US11982544

    申请日：2007-11-02

    申请人： Jack Edward Frayer ,  Y. Y. Ma

    发明人： Jack Edward Frayer ,  Y. Y. Ma

    IPC分类号： G06F12/02 ,  G06F13/14

    CPC分类号： G06F13/4239 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0866 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/154

    摘要： Embodiments of the present invention provides a system controller interfacing point-to-point subsystems consisting of solid state memory. The point-to-point linked subsystems enable high bandwidth data transfer to a system controller. The memory subsystems locally control the normal solid state disk functions. The independent subsystems thus configured and scaled according to various applications enables the memory storage system to operate with optimal data bandwidths, optimal overall power consumption, improved data integrity and increased disk capacity than previous solid state disk implementations.

    摘要翻译： 本发明的实施例提供一种由固态存储器组成的系统控制器接口点对点子系统。 点到点链接的子系统使得能够将高带宽数据传输到系统控制器。 内存子系统本地控制正常的固态磁盘功能。 如此根据各种应用配置和缩放的独立子系统使得存储器存储系统能够以比先前的固态磁盘实现更好的数据带宽，最佳的整体功耗，改进的数据完整性和增加的磁盘容量来运行。