公开(公告)号：US07352623B2

公开(公告)日：2008-04-01

申请号：US11322910

申请日：2005-12-29

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC: G11C11/34

CPC classification number: G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell.

Abstract translation: NOR闪速存储器件包括耦合到配置为响应于字线电压被感测的位线的多电平存储器单元，以及放电电路，被配置为当多电平存储器单元被感测为接通单元时放电位线 。

公开(公告)号：US20070002628A1

公开(公告)日：2007-01-04

申请号：US11322910

申请日：2005-12-29

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell.

Abstract translation: NOR闪速存储器件包括耦合到配置为响应于字线电压被感测的位线的多电平存储器单元，以及放电电路，被配置为当多电平存储器单元被感测为接通单元时放电位线 。

公开(公告)号：US20170294443A1

公开(公告)日：2017-10-12

申请号：US15626395

申请日：2017-06-19

Applicant: JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

Inventor： JONG WON KIM ,  SEUNG HYUN LIM ,  CHANG SEOK KANG ,  YOUNG WOO PARK ,  DAE HOON BAE ,  DONG SEOG EUN ,  WOO SUNG LEE ,  JAE DUK LEE ,  JAE WOO LIM ,  HANMEI CHOI

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11529

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US20170040337A1

公开(公告)日：2017-02-09

申请号：US14987835

申请日：2016-01-05

Applicant: Jong Won KIM ,  Seung Hyun LIM ,  Chang Seok KANG ,  Young Woo PARK ,  Dae Hoon BAE ,  Dong Seog EUN ,  Woo Sung LEE ,  Jae Duk LEE ,  Jae Woo LIM ,  HanMei CHOI

Inventor： Jong Won KIM ,  Seung Hyun LIM ,  Chang Seok KANG ,  Young Woo PARK ,  Dae Hoon BAE ,  Dong Seog EUN ,  Woo Sung LEE ,  Jae Duk LEE ,  Jae Woo LIM ,  HanMei CHOI

IPC: H01L27/115

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract translation: 存储器件包括多个通道区域，每个沟道区域在垂直于衬底的上表面的方向上延伸，多个栅极电极层和堆叠在衬底上的与沟道区相邻的多个绝缘层，每个栅电极 延伸不同长度，以及与多个栅电极层的第一端相邻的多个虚设通道区域，其中所述衬底包括形成在所述多个虚拟通道区域下方的衬底绝缘层。

公开(公告)号：US07480182B2

公开(公告)日：2009-01-20

申请号：US11486227

申请日：2006-07-13

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC: G11C6/06

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

Abstract translation: 通过在存储器单元中编程数据，对存储单元执行虚拟验证操作，并且基于虚拟验证操作的结果对存储器单元执行程序验证操作来验证NOR闪速存储器件的编程操作。

公开(公告)号：US20100010760A1

公开(公告)日：2010-01-14

申请号：US12517801

申请日：2007-09-19

Applicant: Jong Ho Kim ,  Heon Jin Hong ,  Chang Joo Kim ,  Il Suek Koh ,  Jae Woo Lim

Inventor： Jong Ho Kim ,  Heon Jin Hong ,  Chang Joo Kim ,  Il Suek Koh ,  Jae Woo Lim

IPC: G01R13/00

CPC classification number: H04B17/3912

Abstract: Provided is a method for analyzing a reflection wave using effective impedance. The method includes the steps of: a) modeling a reflection surface of a building two-dimensionally; and b) obtaining a reflection wave by radiating a radio wave to the modeled reflection surface and analyzing the obtained reflection wave through making medium uniform.

Abstract translation: 提供了一种使用有效阻抗来分析反射波的方法。 该方法包括以下步骤：a）二维建模建筑物的反射面; b）通过向建模后的反射面照射无线电波来获得反射波，并通过使介质均匀地分析得到的反射波。

公开(公告)号：US20070047320A1

公开(公告)日：2007-03-01

申请号：US11486227

申请日：2006-07-13

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

Abstract translation: 通过在存储器单元中编程数据，对存储单元执行虚拟验证操作，并且基于虚拟验证操作的结果对存储器单元执行程序验证操作来验证NOR闪速存储器件的编程操作。