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    Low cost, high thermal performance package for flip chips with low mechanical stress on chip
    2.
    发明授权
    Low cost, high thermal performance package for flip chips with low mechanical stress on chip 失效
    低成本，高性能封装，用于片上低机械应力的倒装芯片

    公开(公告)号：US5621615A

    公开(公告)日：1997-04-15

    申请号：US415114

    申请日：1995-03-31

    Applicant: Peter F. Dawson, deceased ,  Jacques Leibovitz ,  Voddarahalli K. Nagesh

    Inventor： Peter F. Dawson, deceased ,  Jacques Leibovitz ,  Voddarahalli K. Nagesh

    IPC: H01L23/40 ,  H05K7/10 ,  H05K7/20

    CPC classification number: H01L23/4006 ,  H05K7/1061 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15312 ,  H01L2924/16195

    Abstract: The flip chip package described is comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material, between the first major surface of the die and the first major surface of the heat removal structure, adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.

    Abstract translation: 所述的倒装芯片封装包括衬底，附着于衬底的环结构，散热结构以及与散热结构热耦合的芯片。 包装盖由环形结构和散热结构组成。 将环结构和除热结构分离直到将环结构连接到基底上，使环结构钎焊到基底上。 将环结构钎焊到衬底会降低芯片的机械应力。 在模具的第一主表面和除热结构的第一主表面之间的管芯附着材料将模具粘附并将模具热耦合到除热结构。 芯片附着层具有预定的厚度，从而提供确定的低热阻，使得封装的热性能确定。

    Aluminum nitride multi-chip module
    4.
    发明授权
    Aluminum nitride multi-chip module 失效
    氮化铝多芯片模块

    公开(公告)号：US5155661A

    公开(公告)日：1992-10-13

    申请号：US700784

    申请日：1991-05-15

    Applicant: Voddarahalli K. Nagesh ,  Kim H. Chen

    Inventor： Voddarahalli K. Nagesh ,  Kim H. Chen

    IPC: H05K7/20 ,  H01L23/373 ,  H01L23/40 ,  H05K7/10

    CPC classification number: H05K7/1061 ,  H01L23/3731 ,  H01L23/4006 ,  H01L2023/4062 ,  H01L2023/4087 ,  H01L2924/0002

    Abstract: A multi-chip module is configured using an aluminum nitride, or AlN, multi-chip substrate, sandwiched chip side down under an extruded aluminum convection cooled heat sink. An alignment ring includes grooves for control of z-axis elastomeric conductors slightly compressed between the chip connection surface of the substrate and the top surface of a PCB to provide the interconnections therebetween. The alignment ring includes a stopper portion which controls the height of the heat sink above the PCB as well as a smaller rail portion which controls the height of the substrate above the PCB. The good thermal conductivity, ruggedness and relatively good TCE match of the AlN substrate to the silicon chips permits a convenient, dense and thermally rugged MCM.

    Abstract translation: 多芯片模块使用氮化铝或AlN多芯片衬底，在挤压的铝对流冷却散热片下方夹着芯片侧面。 对准环包括用于控制在基板的芯片连接表面和PCB的顶表面之间稍微压缩的z轴弹性体导体的凹槽，以提供它们之间的互连。 对准环包括控制PCB上方的散热器的高度的止动部分以及控制PCB上方的基板的高度的较小的轨道部分。 AlN衬底与硅芯片的良好的导热性，坚固性和较好的TCE匹配能够使MCM方便，密集和耐热。

    Reliable low thermal resistance package for high power flip clip ICs
    5.
    发明授权
    Reliable low thermal resistance package for high power flip clip ICs 失效
    适用于大功率倒装夹IC的可靠低热阻封装

    公开(公告)号：US5585671A

    公开(公告)日：1996-12-17

    申请号：US319764

    申请日：1994-10-07

    Applicant: Voddarahalli K. Nagesh ,  Kim H. Chen ,  Cheng-Cheng Chang ,  Bahram Afshari ,  Jacques Leibovitz

    Inventor： Voddarahalli K. Nagesh ,  Kim H. Chen ,  Cheng-Cheng Chang ,  Bahram Afshari ,  Jacques Leibovitz

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/10 ,  H01L23/34

    CPC classification number: H01L23/3675 ,  H01L23/367 ,  H01L23/3737 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253

    Abstract: A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40). An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material (18), to define the minimum final thickness (40) of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.

    Abstract translation: 倒装芯片IC封装（10）通过预定厚度范围的管芯附着层（18）提供安装在芯片（12）背面的导热盖（20）。 在盖子（20）上形成一个边缘（22），其深度（44）小于芯片厚度（16）和互连件（16）的总和（42） 芯片附着层（18）的最终厚度（40）预定的边缘（46）。 将热填充环氧树脂的初始厚度施加到芯片的背面，并且将盖子附着环氧树脂层（24）以足以跨越预定边缘的厚度施加到盖的边缘。 盖子悬挂在芯片附着层（18）上，盖子的边缘围绕着芯片并漂浮在盖子附着材料上。 盖子以足以在小于初始厚度并且不小于最小最终厚度（40）的范围内将管芯附接材料压缩到预定厚度的力夹紧在芯片上。 在边缘的底面上形成氧化物层，例如铁或铁 - 合金氧化物层。 间隔件被放置在芯片附接材料（18）内的芯片的背面，以限定芯片附着层的最小最终厚度（40）。 在盖子上形成一个倾斜或有级的通风孔，并将其密封。

    Method for preparing a thick film conductor
    7.
    发明授权
    Method for preparing a thick film conductor 失效
    制备厚膜导体的方法

    公开(公告)号：US4130671A

    公开(公告)日：1978-12-19

    申请号：US838273

    申请日：1977-09-30

    Applicant: Voddarahalli K. Nagesh ,  Richard M. Fulrath, deceased

    Inventor： Voddarahalli K. Nagesh ,  Richard M. Fulrath, deceased

    IPC: H01B1/16 ,  H05K1/09 ,  B05D5/12 ,  C03C15/00 ,  C03C17/06

    CPC classification number: H01B1/16 ,  H05K1/092

    Abstract: A method for preparing a thick film conductor which comprises providing surface active glass particles, mixing the surface active glass particles with a thermally decomposable organometallic compound, for example, a silver resinate, and then decomposing the organometallic compound by heating, thereby chemically depositing metal on the glass particles. The glass particle mixture is applied to a suitable substrate either before or after the organometallic compound is thermally decomposed. The resulting system is then fired in an oxidizing atmosphere, providing a microstructure of glass particles substantially uniformly coated with metal.

    Abstract translation: 一种制备厚膜导体的方法，包括提供表面活性玻璃颗粒，将表面活性玻璃颗粒与可热分解的有机金属化合物例如树脂树脂混合，然后通过加热分解有机金属化合物，从而将金属化学沉积在 玻璃颗粒。 在有机金属化合物被热分解之前或之后，将玻璃颗粒混合物施加到合适的基材上。 然后将所得体系在氧化气氛中焙烧，提供基本上均匀涂覆有金属的玻璃颗粒的微结构。

    Controlled etching process for forming fine-geometry circuit lines on a substrate
    10.
    发明授权
    Controlled etching process for forming fine-geometry circuit lines on a substrate 失效
    用于在基板上形成精细几何电路线的受控蚀刻工艺

    公开(公告)号：US5221421A

    公开(公告)日：1993-06-22

    申请号：US857209

    申请日：1992-03-25

    Applicant: Jacques Leibovitz ,  Daniel J. Miller ,  Maria L. Cobarruviaz ,  John P. Scalia ,  Howard H. Nakano ,  Voddarahalli K. Nagesh ,  Clinton C. Chao

    Inventor： Jacques Leibovitz ,  Daniel J. Miller ,  Maria L. Cobarruviaz ,  John P. Scalia ,  Howard H. Nakano ,  Voddarahalli K. Nagesh ,  Clinton C. Chao

    IPC: C23F1/02 ,  C23F1/46 ,  H01L21/48

    CPC classification number: H01L21/4846 ,  C22B11/046 ,  C23F1/46 ,  Y02P10/214

    Abstract: A specialized etching method for producing fine-geometry gold circuit structures. Production thereof is accomplished by maintaining a constant gold etching rate. Metal etching normally slows as the amount of dissolved gold (a reaction product of the etching process) increases. To remove the dissolved gold, one method involves cooling the etchant to precipitate a gold complex therefrom. The remaining, recovered etchant is then heated and made available for continued etching. Another method involves a cathode/anode assembly which is immersed in the etchant. Activation of the assembly recovers metallic gold and regenerates the etchant. These methods, when used continuously or periodically in a dip or spray etching system, maintain a constant etching rate. As a result, fine-geometry circuit structures may be accurately produced while minimizing material costs (e.g. etchant use) and minimizing the production of undesirable waste products and disposal expenses associated therewith.

    Abstract translation: 一种用于生产精细几何金电路结构的专用蚀刻方法。 通过保持恒定的金蚀刻速率来实现其生产。 随着溶解金（蚀刻工艺的反应产物）的量增加，金属蚀刻通常会减慢。 为了除去溶解的金，一种方法包括冷却蚀刻剂以从其中沉淀出金络合物。 然后将剩余的回收的蚀刻剂加热并用于继续蚀刻。 另一种方法涉及浸入蚀刻剂中的阴极/阳极组件。 组装的激活恢复金属金并再生蚀刻剂。 这些方法当在浸渍或喷涂蚀刻系统中连续或周期地使用时，保持恒定的蚀刻速率。 结果，精细几何电路结构可以精确地产生，同时最小化材料成本（例如蚀刻剂使用）并最小化不合需要的废产物的生产和与之相关的处置费用。

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